4.4 GS/s 220 MHz ΣΔ ADC，带线性化后门控制GmC滤波器

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185281

Julius Edler, Marcel Runge, Sebastian Linnhoff, F. Gerfers

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引用次数: 0

摘要

本文提出了一种4.4 GS/s220Mhz带宽的连续时间σ δ调制器，该调制器具有线性GmC环滤波器，通过多比特反馈实现电压跟踪，并采用后门节点的有源线性化方案。辅助放大器驱动主差分对的后门节点线性化整个$\ mathm {G}_{\ mathm {m}}(\ mathm {V}_{\ mathm {i}\ mathm {n}}$)曲线。制作的原型显示，三阶互调(IM3)产品降低27dB，降至-78dBc, SNDR为62dB，功耗为22 mW，达到优异的49fJ/阶跃功率效率。

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A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter

This paper presents a 4.4 GS/s220Mhz bandwidth continuous time sigma delta modulator with a linear GmC loop filter enabled by voltage tracking through multi-bit feedback and an active linearization scheme employing the back-gate node. An auxiliary amplifier drives the back-gate node of the main differential pair to linearize the overall $\mathrm{G}_{\mathrm{m}}(\mathrm{V}_{\mathrm{i}\mathrm{n}}$) curve. The fabricated prototype shows a 27dB reduction in third order intermodulation (IM3) products down to -78dBc and a SNDR of 62dB while consuming 22 mW, reaching excellent 49fJ/step power efficiency.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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