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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing 使用交叉耦合微电极阵列和二维码分复用的1024通道，64互连，电容性神经接口
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185425
Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, Seonghwan Cho, Taekwang Jang
{"title":"A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing","authors":"Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, Seonghwan Cho, Taekwang Jang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185425","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185425","url":null,"abstract":"This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves $9.7 mu mathrm{W}$ power/ch and 0.005mm2 area/ch efficiency with the highest electrode density of 10,000mm-2, and the fewest interconnects to the authors’ best knowledge.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128594333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs 短沟道体mosfet低温工作低频噪声源的确定
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185298
Takumi Inaba, H. Oka, H. Asai, H. Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, K. Fukuda, Takahiro Mori
{"title":"Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs","authors":"Takumi Inaba, H. Oka, H. Asai, H. Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, K. Fukuda, Takahiro Mori","doi":"10.23919/VLSITechnologyandCir57934.2023.10185298","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185298","url":null,"abstract":"For the first time, we clarified the low-frequency noise source of short-channel bulk MOSFETs at cryogenic temperature. We experimentally revealed that, with decreasing temperature, noise sources transition from inner-oxide traps to interface traps and then to band-edge localized states that have energy levels within a few tenths of meV from the conduction band-edge. This transition occurs because the Fermi level at the interface shifts to near the conduction band, resulting in charge traps responsible for the noise being filled and shallower energy traps contributing to the noise. Determining the noise sources is a critical step in increasing the coherence time of qubits and realizing practical quantum computers with silicon.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124601595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing 4.8mW, 800Mbps混合加密SoC用于后量子安全神经接口
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185393
Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang
{"title":"A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing","authors":"Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185393","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185393","url":null,"abstract":"This work presents the world’s first post-quantum hybrid crypto SoC that achieves an 800Mpbs throughput and consumes only 4. 8mW for remote neural interfacing. The chip dissipates 0.70$mu$J/OP for the handshake and 48pJ/B for data encryption in 40nm CMOS. Flexible authenticated encryption is supported. This work achieves 3-175x higher area efficiency with 16-41x less energy than state-of-the-art designs.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127645141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology Technical Session 技术技术会议
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/vlsitechnologyandcir57934.2023.10185333
{"title":"Technology Technical Session","authors":"","doi":"10.23919/vlsitechnologyandcir57934.2023.10185333","DOIUrl":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185333","url":null,"abstract":"","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127965490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET 基于12nm CMOS FinFET的0.32pJ/b 90Gbps PAM4光接收机前端自动增益控制
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185378
M. Kashani, H. Shakiba, A. Sheikholeslami
{"title":"A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET","authors":"M. Kashani, H. Shakiba, A. Sheikholeslami","doi":"10.23919/VLSITechnologyandCir57934.2023.10185378","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185378","url":null,"abstract":"This work presents a 0.32pJ/b90Gbps PAM4 optical receiver (RX) front-end with a 13.4pA/$sqrt{}$Hz noise density. The proposed design employs a new transimpedance amplifier (TIA) and a single-ended-to-differential (S2D) block providing a large gain-bandwidth product with less power and area overhead compared to the conventional designs. The proposed RX is implemented in 12nm CMOS FinFET process and co-packaged with a commercial photodiode (PD), offering the best power efficiency, input-referred noise, and figure-of-merit (FOM) amongst the previous state-of-the-art designs [1] –[5].","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121691195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 16-channel Active-Matrix Mini-LED Driver with an USI-B for EMI noise reduction 一个带USI-B的16通道有源矩阵迷你led驱动器，用于EMI降噪
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185271
Y. Kwon, Y. Kwak, Y. Choi, K. Kim, S. Kim, W. Jang, J. Park, K. Ryu, S. Yoo, H. Lim, J. Lee
{"title":"A 16-channel Active-Matrix Mini-LED Driver with an USI-B for EMI noise reduction","authors":"Y. Kwon, Y. Kwak, Y. Choi, K. Kim, S. Kim, W. Jang, J. Park, K. Ryu, S. Yoo, H. Lim, J. Lee","doi":"10.23919/VLSITechnologyandCir57934.2023.10185271","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185271","url":null,"abstract":"It is presented the first active-matrix (AM) mini light-emitting diode (LED) driver system for a back-light unit (BLU) that uses a newly proposed 1-pair clock-embedding unified standard interface (USI-B) to reduce EMI and power consumption. The system consists of a pixel driver IC (PDIC) and a pixel IC (PIC). The PDIC transmits 20-bit brightness data to the PIC to control the mini-LEDs. The USI-B, based on clock and data recovery (CDR), has been applied to enhance high-level noise tolerance, long-distance transmission, and EMI reduction. Self-current calibration and offset cancellation in the PIC allow for current accuracy of up to ±1% between PICs. This system can support 16,128 LED local-dimming zones (LDZ) using two PDIC and has a measured EMI level of less than 30dB($mu$V/m). The PDIC and PIC were fabricated using a 65nm and 130nm CMOS process, respectively.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132223205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision 基于12 nm 0.62-1.61 mW超低功耗数字cim的端到端始终在线视觉深度学习系统
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185296
En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-CL Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen
{"title":"A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision","authors":"En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-CL Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen","doi":"10.23919/VLSITechnologyandCir57934.2023.10185296","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185296","url":null,"abstract":"This work proposes an ultra-low power DCIM-based DL system (DCIM-DLS) for end-to-end AoV with the power range from 0.62 to 1.61 mW (INT8, 2-15 fps). Compared to the prior art [3], the power consumption of DCIM-DLS can be reduced by 70.9% based on the following techniques: 1) an area and energy efficient DCIM that reduces compute RC loading by using pushed-rule 2p8T SRAM bitcell with folded kernels selector, 2) a DCIM-friendly dataflow strategy with dual accumulators that minimizes the DCIM power of weight update and avoids redundant data movement for power saving, and 3) a reconfigurable DCIM control scheme that supports mixed-precision to further reduce power consumption.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope 在3.4 ghz啁啾带宽和960 mhz /μs啁啾斜率下实现0.034% RMS频率误差的11.4 ~ 16.4 ghz带周期滑动补偿和反向跟踪DPD的FMCW数字锁相环
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185335
Angxiao Yan, W. Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, B. Chi
{"title":"An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope","authors":"Angxiao Yan, W. Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, B. Chi","doi":"10.23919/VLSITechnologyandCir57934.2023.10185335","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185335","url":null,"abstract":"This article introduces a digital FMCW PLL with cycle-slipping compensation scheme and wideband digital-to-time converter (DTC) gain calibration to break the limitation of the maximum trackable chirp slope for two-point modulation (TPM) FMCW PLLs. In addition, FM error is minimized by the proposed back-tracking digital-pre-distortion (DPD) scheme. As far as the authors are aware, the proposed FMCW PLL achieves the widest normalized chirp bandwidth and the fastest normalized chirp slope concurrently while retaining decent chirp linearity.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"29 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132810844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit designs for practical-scale fault-tolerant quantum computing 实际规模容错量子计算电路设计
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185351
Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto
{"title":"Circuit designs for practical-scale fault-tolerant quantum computing","authors":"Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto","doi":"10.23919/VLSITechnologyandCir57934.2023.10185351","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185351","url":null,"abstract":"To demonstrate reliable and scalable quantum computation, we need quantum error correction to reduce its error rates. One of the most challenging parts of implementing quantum error correction is to design error-decoding units, which estimate errors during computation. We estimate the required performances of error-decoding units to run practical-scale quantum algorithms and discuss the directions to satisfy them.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Searching for Nonlinearity: Scaling Limits in NAND Flash 非线性搜索:NAND闪存的缩放限制
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185165
S. Sivaram, A. Ilkbahar
{"title":"Searching for Nonlinearity: Scaling Limits in NAND Flash","authors":"S. Sivaram, A. Ilkbahar","doi":"10.23919/VLSITechnologyandCir57934.2023.10185165","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185165","url":null,"abstract":"Data generation is growing at an exponential rate and the market opportunity for data storage is vast. However, there is still a substantial difference in the amount of data created versus data stored, driven by price elasticity of demand in the storage media. Pricing lies in the balance of supply and demand, but for NAND manufacturers to be profitable, cost is the driver for consistent price decline and will ultimately determine the amount of data stored. In this talk, we show that as NAND Flash moves into a mature era of 3D scaling using only increasing layer count results in a sub-linear cost reduction while producing higher bit growth. This breaks the virtuous cycle of growth, producing more bits than the market can absorb at a given price point and challenges the affordability of future investments. NAND scaling needs to move away from solely increasing layer count and instead seeking new avenues for reducing cost and complexity. Equipment productivity and reduction in consumables remain critical focus areas for the supply chain to contribute to cost reduction. Wafer bonding technology can be an enabler for new opportunities. It allows for decoupling the memory array from complex logic circuits, allowing new high speed logic integration with the memory layers, and simplifying manufacturing cycle times. This technology also allows the industry to move away from a one-size-fits-all NAND die to customized solutions for various applications and system level savings. Despite such breakthroughs, ultimately the health of the storage industry will be determined by fair distribution of the profit pool across the value chain commensurate with the R&D and capital spending by the different players.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127392174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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