在3.4 ghz啁啾带宽和960 mhz /μs啁啾斜率下实现0.034% RMS频率误差的11.4 ~ 16.4 ghz带周期滑动补偿和反向跟踪DPD的FMCW数字锁相环

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185335

Angxiao Yan, W. Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, B. Chi

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引用次数: 0

摘要

本文介绍了一种采用周期滑动补偿方案和宽带数字时转换器(DTC)增益校准的数字FMCW锁相环，以突破两点调制(TPM) FMCW锁相环最大可跟踪啁啾斜率的限制。此外，所提出的反向数字预失真(DPD)方案使调频误差最小化。据作者所知，所提出的FMCW锁相环在保持良好的啁啾线性度的同时，实现了最宽的归一化啁啾带宽和最快的归一化啁啾斜率。

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An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope

This article introduces a digital FMCW PLL with cycle-slipping compensation scheme and wideband digital-to-time converter (DTC) gain calibration to break the limitation of the maximum trackable chirp slope for two-point modulation (TPM) FMCW PLLs. In addition, FM error is minimized by the proposed back-tracking digital-pre-distortion (DPD) scheme. As far as the authors are aware, the proposed FMCW PLL achieves the widest normalized chirp bandwidth and the fastest normalized chirp slope concurrently while retaining decent chirp linearity.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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