4.8mW, 800Mbps混合加密SoC用于后量子安全神经接口

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185393

Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang

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引用次数: 0

摘要

这项工作提出了世界上第一个后量子混合加密SoC，实现了800Mpbs的吞吐量，仅消耗4。8mW用于远程神经接口。该芯片用于握手的功耗为0.70$\mu$J/OP，用于40nm CMOS数据加密的功耗为48pJ/B。支持灵活的身份验证加密。与最先进的设计相比，这项工作的面积效率提高了3-175倍，能耗减少了16-41倍。

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A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing

This work presents the world’s first post-quantum hybrid crypto SoC that achieves an 800Mpbs throughput and consumes only 4. 8mW for remote neural interfacing. The chip dissipates 0.70$\mu$J/OP for the handshake and 48pJ/B for data encryption in 40nm CMOS. Flexible authenticated encryption is supported. This work achieves 3-175x higher area efficiency with 16-41x less energy than state-of-the-art designs.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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