Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, Seonghwan Cho, Taekwang Jang
{"title":"使用交叉耦合微电极阵列和二维码分复用的1024通道,64互连,电容性神经接口","authors":"Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, Seonghwan Cho, Taekwang Jang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185425","DOIUrl":null,"url":null,"abstract":"This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves $9.7 \\mu \\mathrm{W}$ power/ch and 0.005mm2 area/ch efficiency with the highest electrode density of 10,000mm-2, and the fewest interconnects to the authors’ best knowledge.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing\",\"authors\":\"Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, Seonghwan Cho, Taekwang Jang\",\"doi\":\"10.23919/VLSITechnologyandCir57934.2023.10185425\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves $9.7 \\\\mu \\\\mathrm{W}$ power/ch and 0.005mm2 area/ch efficiency with the highest electrode density of 10,000mm-2, and the fewest interconnects to the authors’ best knowledge.\",\"PeriodicalId\":317958,\"journal\":{\"name\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185425\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185425","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing
This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves $9.7 \mu \mathrm{W}$ power/ch and 0.005mm2 area/ch efficiency with the highest electrode density of 10,000mm-2, and the fewest interconnects to the authors’ best knowledge.