A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing

Abstract

This work presents the world’s first post-quantum hybrid crypto SoC that achieves an 800Mpbs throughput and consumes only 4. 8mW for remote neural interfacing. The chip dissipates 0.70$\mu$J/OP for the handshake and 48pJ/B for data encryption in 40nm CMOS. Flexible authenticated encryption is supported. This work achieves 3-175x higher area efficiency with 16-41x less energy than state-of-the-art designs.