Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jungjune Park, Tae-Sung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, C. Lee, Young-Dong Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, Jaehwan Kim, Hyojin Kwon, Chan-ho Kim, M. Jung, Chanjin Park, Don-Iru Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur
{"title":"3.0 Gb/s/pin的第四代F-chip与Toggle 5.0规格的16Tb NAND闪存多芯片封装","authors":"Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jungjune Park, Tae-Sung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, C. Lee, Young-Dong Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, Jaehwan Kim, Hyojin Kwon, Chan-ho Kim, M. Jung, Chanjin Park, Don-Iru Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur","doi":"10.23919/VLSITechnologyandCir57934.2023.10185391","DOIUrl":null,"url":null,"abstract":"A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3rd generation F-chip.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package\",\"authors\":\"Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jungjune Park, Tae-Sung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, C. Lee, Young-Dong Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, Jaehwan Kim, Hyojin Kwon, Chan-ho Kim, M. Jung, Chanjin Park, Don-Iru Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur\",\"doi\":\"10.23919/VLSITechnologyandCir57934.2023.10185391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3rd generation F-chip.\",\"PeriodicalId\":317958,\"journal\":{\"name\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package
A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3rd generation F-chip.
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