一种数据速率高达15Gb/s的HBM低电压区域高效TSV I/O，具有重叠复用驱动、ISI补偿器和QEC

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185328

Taeryeong Kim, Ji-Young Kim, J. You, Hohyun Chae, B. Moon, Kyomin Sohn, Seong-ook Jung

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引用次数: 0

摘要

本文提出了一种利用重叠多路复用驱动、ISI补偿器(混合均衡器、直接反馈1分频DFE)和正交误差校正器的高带宽存储器的低电压面积高效通硅孔(TSV) I/O。所提出的TSV I/O在65nm CMOS工艺中采用模拟的12层TSV实现。测量结果表明，在15Gb/s时，PRBS-31的能量效率为0.145pJ/b/pF，时间裕度为30%，误码率为10 ^{-12}$。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER $\lt 10 ^{-12}$ at 15Gb/s with PRBS-31.

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来源期刊

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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