Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture

Abstract

In this work, we report a monolithically 3D integration of HfZrOx (HZO) ferroelectric FET (FeFET), analog computing-in-memory (CIM), hybrid back-end-of-line (BEOL) CMOS on top of standard Si-CMOS technology, namely M3D-FACT. The 1st layer is Si CMOS circuits for control logic, and the 2nd layer is an analog resistive random-access memory (RRAM) array for CIM. The 3rd layer is a reconfigurable datapath (RCD), consisting of FeFETs with InGaZnOx (IGZO) channel and hybrid CMOS logic based on carbon nanotube (CNT) PMOS and IGZO NMOS. The structure and functions of each layer were verified. Furthermore, a reconfigurable CIM architecture was implemented using the M3D-FACT chip, and the system-level benchmark against its 2D counterpart shows higher energy efficiency in three different network models (6.9$\times $ for VGG-8, 19.2$\times$ for DenseNet-121, and 9.9$\times$ for ResNet-18).