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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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Wireless Body-Area Network Transceiver ICs with Concurrent Body-Coupled Powering and Communication using Single Electrode 无线体域网络收发器集成电路的并发体耦合供电和通信使用单电极
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185270
Jiamin Li, Yilong Dong, Longyang Lin, Joanne Si Ying Tan, Fong Jia Yi, Jerald Yoo
{"title":"Wireless Body-Area Network Transceiver ICs with Concurrent Body-Coupled Powering and Communication using Single Electrode","authors":"Jiamin Li, Yilong Dong, Longyang Lin, Joanne Si Ying Tan, Fong Jia Yi, Jerald Yoo","doi":"10.23919/VLSITechnologyandCir57934.2023.10185270","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185270","url":null,"abstract":"We propose the wireless body-coupled power (BCP) transfer ICs with concurrent body-coupled communication (BCC) via a single electrode. Base Station (BS) IC employs the adaptive Self-Interference Cancellation for >40dB signal suppression and a Charge Replenishing HV driver for 31% power saving. Sensor Node (SN) IC adopts ground-domain separation with 89.1% cross-ground-domain power efficiency. The ICs in 40nm standard CMOS deliver power with concurrent data uplink and downlink to the entire body area.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
216 fps 672 × 512 pixel 3 μm Indirect Time-of-Flight Image Sensor with 1-Frame Depth Acquisition for Motion Artifact Suppression 216 fps 672 × 512像素3 μm具有1帧深度采集的间接飞行时间图像传感器用于运动伪影抑制
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185332
Chihiro Okada, S. Yokogawa, Y. Yorikado, K. Honda, Naoki Okuno, Ryohei Ikeno, Makoto Yamakoshi, Hiroshi Ito, Shohei Yoshitsune, Masatsugu Desaki, Shota Hida, Atsushi Nose, H. Wakabayashi, F. Koga
{"title":"216 fps 672 × 512 pixel 3 μm Indirect Time-of-Flight Image Sensor with 1-Frame Depth Acquisition for Motion Artifact Suppression","authors":"Chihiro Okada, S. Yokogawa, Y. Yorikado, K. Honda, Naoki Okuno, Ryohei Ikeno, Makoto Yamakoshi, Hiroshi Ito, Shohei Yoshitsune, Masatsugu Desaki, Shota Hida, Atsushi Nose, H. Wakabayashi, F. Koga","doi":"10.23919/VLSITechnologyandCir57934.2023.10185332","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185332","url":null,"abstract":"A 216 fps, 672 × 512 pixel, 3 μm indirect time-of-flight image sensor with 1-frame depth acquisition for motion artifact suppression was developed for versatile applications. To suppress motion artifacts, we employed a floating diffusion sharing circuit, vertical gate technology for the transfer gate, and IQ mosaic pixel coding with demosaic processing. Consequently, a motion artifact-free depth map was obtained, with a 3.5 times faster frame rate, 50% lower power, and 71% lower readout noise compared to a conventional 4-frame sensor.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116427374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET 基于采样无偏置RC电路和动态功率缩放的6nW 30.8kHz弛豫振荡器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185329
Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao
{"title":"A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET","authors":"Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao","doi":"10.23919/VLSITechnologyandCir57934.2023.10185329","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185329","url":null,"abstract":"An ultra-low power 30.8kHz relaxation oscillator (RxO) is presented. To achieve low power consumption, a sampling bias-free RC circuit is proposed and leveraged in a frequencylock-loop. Moreover, dynamic power scaling is implemented by adopting local phase allocation and global duty control. In this work, the RxO consumes only 6.05nW under a 0.7V supply. The FoM achieves 0.196nW/kHz, and the active area of RxO occupies 0.063mm 2 in a 12nm FinFET process.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121464698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration Arvon:一款异构SiP协议，集成14nm FPGA和两个22nm 1.8TFLOPS/W dsp和1.7Tbps/mm2 AIB 2.0接口，提供多功能工作负载加速
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185388
Wei Tang, Sung-gun Cho, T. Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, S. Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
{"title":"Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration","authors":"Wei Tang, Sung-gun Cho, T. Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, S. Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185388","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185388","url":null,"abstract":"Arvon is a heterogeneous system in a package (SiP) that integrates a 14nm FPGA chiplet with two dense and efficient 22nm DSP chiplets through Embedded Multi-die Interconnect Bridges (EMIBs) as illustrated in Fig. 1. The chiplets communicate via a 1.536Tbps Advanced Interface Bus (AIB) 1.0 interface and a 7.68Tbps AIB 2.0 interface. We demonstrate the first-ever AIB 2.0 I/O prototype using $36 mu mathrm{m}$-pitch microbumps, achieving 4Gbps/pin at 0.10pJ/b (0.46pJ/b including adapter), and a bandwidth density of 1.024Tbps/mm-shoreline and 1.705Tbps/mm2-area. Arvon is programmable, supporting workloads from neural network (NN) to communication processing (comm) and providing a peak performance of 4.14TFLOPS (FP16, half-precision floating-point) by each DSP chiplet at 1.8TFLOPS/W. A compilation flow is developed to map workloads across FPGA and DSPs to optimize performance and utilization.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink 一种基于无源Boxcar集成和多级数据链的微波束成形adc的三维超声音高匹配收发专用集成电路
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185159
P. Guo, Z. Chang, Emile Noothout, H. Vos, J. Bosch, N. D. Jong, M. Verweij, M. Pertijs
{"title":"A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink","authors":"P. Guo, Z. Chang, Emile Noothout, H. Vos, J. Bosch, N. D. Jong, M. Verweij, M. Pertijs","doi":"10.23919/VLSITechnologyandCir57934.2023.10185159","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185159","url":null,"abstract":"This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming $(mu$ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The $mu$ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications 2nm节点高性能计算和移动SoC应用的前端和后端功率传输网络指南
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185394
J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, R. Baek
{"title":"Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications","authors":"J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, R. Baek","doi":"10.23919/VLSITechnologyandCir57934.2023.10185394","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185394","url":null,"abstract":"For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $lt 5.9%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $lt 10.9%$ for HPCs, to be cost-effective at similar IR drop.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications 一种65nm 60mW双环自适应数字波束形成器，具有优化的旁瓣抵消和片上DOA估计，适用于毫米波应用
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185316
Sigang Ryu, A. S. Assoa, Shota Konno, A. Raychowdhury
{"title":"A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications","authors":"Sigang Ryu, A. S. Assoa, Shota Konno, A. Raychowdhury","doi":"10.23919/VLSITechnologyandCir57934.2023.10185316","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185316","url":null,"abstract":"This paper demonstrates an mm-wave baseband digital beamformer that fully integrates an adaptive sidelobe canceller and on-chip direction of arrival (DOA) estimation. To achieve high energy-efficiency, the DOA estimation loop preemptively adjusts the weights of the phase rotators at the front of the SAR-ADCs, which enables the sidelobe cancellation loop to be implemented with a straightforward structure. For efficient ESPRIT DOA estimation, CORDIC-based QR-iteration is employed to solve eigenvalue decomposition, thus circumventing the need for complex matrix computation. The adaptive beamformer implemented in 65nm CMOS dissipates 60mW at 100MHz while occupying 0.64mm 2 on-chip area. The energy efficiency is 600(330) pJ/symbol with (without) DOA estimation.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133627350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C 高温GaN-on-Si技术中的DTCO: 300°C的算术逻辑单元和高达500°C的CAD框架
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185364
Q. Xie, M. Yuan, J. Niroula, Bejoy Sikder, S. Luo, K. Fu, N. Rajput, Ayan Biswas Pranta, Pradyot Yadav, Yuji Zhao, N. Chowdhury, Tomás Palacios
{"title":"Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C","authors":"Q. Xie, M. Yuan, J. Niroula, Bejoy Sikder, S. Luo, K. Fu, N. Rajput, Ayan Biswas Pranta, Pradyot Yadav, Yuji Zhao, N. Chowdhury, Tomás Palacios","doi":"10.23919/VLSITechnologyandCir57934.2023.10185364","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185364","url":null,"abstract":"This article reports advances in high temperature (HT) GaNon-Si technology by taking pioneering steps towards design technology co-optimization (DTCO). A computer-aided design (CAD) framework was established and experimentally validated up to $500 ^{circ}mathrm{C}$, the highest temperature achieved by such a framework for GaN technology. This framework was made possible thanks to (1) demonstration of multiple key functional building blocks (e.g. arithmetic logic unit (ALU)) by the proposed technology at HT; (2) experimentally calibrated transistor compact models up to $500 ^{circ}mathrm{C}($ highest temperature modeled for an Enhancement-mode GaN transistor). Excellent agreement was achieved between experimental and simulated circuits in the static characteristics (<0.1V difference in voltage swing) and trends of dynamic characteristics (timing) were accurately captured. By adopting complementary approaches in experiment and simulation, this work lays the foundation for the scaling-up of HT GaN-on-Si technology for mixed-signal applications of HT (> 300 °C) electronics.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology 采用5nm技术实现双泵读写同周期的4.24GHz 128X256 SRAM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185268
Nick Zhang, Young Suk Kim, P. Hsu, Sam-Soo Kim, Derek Tao, H. Liao, Ping-Wei Wang, G. Yeap, Quincy Li, Tsung-Yung Jonathan Chang
{"title":"A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology","authors":"Nick Zhang, Young Suk Kim, P. Hsu, Sam-Soo Kim, Derek Tao, H. Liao, Ping-Wei Wang, G. Yeap, Quincy Li, Tsung-Yung Jonathan Chang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185268","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185268","url":null,"abstract":"A high speed IRIW two port 32Kbit (128×256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with TRKBL bypassing is proposed to enhance read performance. Double metal scheme is applied to improve signal integrity and overall operating cycle time. A Local Interlock Circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. The silicon results show that the slow corner wafer was able to achieve 4. 24GHz at 1.0V/100°C in 5nm FinFET technology.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array 一种用于ka波段位-射频并发多波束DBF阵列的全数字同相发射机IC
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185304
Dong Wang, Jiazheng Zhou, Hui Xu, Ningyuan Zhang, Xiaolei Su, Zhengkun Shen, Haoyun Jiang, Fan Yang, Yixiao Wang, Junhua Liu, H. Liao
{"title":"An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array","authors":"Dong Wang, Jiazheng Zhou, Hui Xu, Ningyuan Zhang, Xiaolei Su, Zhengkun Shen, Haoyun Jiang, Fan Yang, Yixiao Wang, Junhua Liu, H. Liao","doi":"10.23919/VLSITechnologyandCir57934.2023.10185304","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185304","url":null,"abstract":"The first Ka-band DTX-based bit-to-RF multi-beam transmitter array is demonstrated in this work. The DTX IC features a prototype digital outphasing architecture with a 4x frequency multiplication scheme and a piecewise varactor array (PVA) linearization technique. Further, a compact wideband ADPLL with 24-bit phase shifting is integrated, eliminating the high-frequency LO distribution and improving the phase/gain alignment in the array. Leveraging these techniques, a low-cost 24.5-30GHz DTX is fabricated in 40nm CMOS. It achieves an EVM of-24.2dB for 16QAM without calibration and only occupies a core area of 1.2 x1.35mm2. Bit-to-RF concurrent multi-beam forming is demonstrated with a lx8 uniform linear array (ULA) and the best normalized energy/area efficiency are achieved.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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