Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C

Abstract

This article reports advances in high temperature (HT) GaNon-Si technology by taking pioneering steps towards design technology co-optimization (DTCO). A computer-aided design (CAD) framework was established and experimentally validated up to $500 ^{\circ}\mathrm{C}$, the highest temperature achieved by such a framework for GaN technology. This framework was made possible thanks to (1) demonstration of multiple key functional building blocks (e.g. arithmetic logic unit (ALU)) by the proposed technology at HT; (2) experimentally calibrated transistor compact models up to $500 ^{\circ}\mathrm{C}($ highest temperature modeled for an Enhancement-mode GaN transistor). Excellent agreement was achieved between experimental and simulated circuits in the static characteristics (<0.1V difference in voltage swing) and trends of dynamic characteristics (timing) were accurately captured. By adopting complementary approaches in experiment and simulation, this work lays the foundation for the scaling-up of HT GaN-on-Si technology for mixed-signal applications of HT (> 300 °C) electronics.