2nm节点高性能计算和移动SoC应用的前端和后端功率传输网络指南

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185394

J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, R. Baek

{"title":"2nm节点高性能计算和移动SoC应用的前端和后端功率传输网络指南","authors":"J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, R. Baek","doi":"10.23919/VLSITechnologyandCir57934.2023.10185394","DOIUrl":null,"url":null,"abstract":"For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2\\mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $\\lt 5.9\\%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $\\lt 10.9\\%$ for HPCs, to be cost-effective at similar IR drop.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications\",\"authors\":\"J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, R. Baek\",\"doi\":\"10.23919/VLSITechnologyandCir57934.2023.10185394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2\\\\mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $\\\\lt 5.9\\\\%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $\\\\lt 10.9\\\\%$ for HPCs, to be cost-effective at similar IR drop.\",\"PeriodicalId\":317958,\"journal\":{\"name\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

我们首次提出了在$2\ mathm {~nm}$节点中使用前端(FS)或后端(BS)供电网络(PDN)的选择指南。分析了各种FS和BS-PDN结构在高性能计算(HPC)和移动SoC应用中的IR下降。对于移动soc来说，BS-PDN的附加工艺成本(PC)应该是基于纳米片FET (NSFET)的前端成本的5.9%，但对于高性能PC来说，要在类似IR下降的情况下具有成本效益，则要高得多。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications

For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2\mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $\lt 5.9\%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $\lt 10.9\%$ for HPCs, to be cost-effective at similar IR drop.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

自引率

0.00%

发文量