采用5nm技术实现双泵读写同周期的4.24GHz 128X256 SRAM

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185268

Nick Zhang, Young Suk Kim, P. Hsu, Sam-Soo Kim, Derek Tao, H. Liao, Ping-Wei Wang, G. Yeap, Quincy Li, Tsung-Yung Jonathan Chang

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引用次数: 0

摘要

提出了一种高速irw双端口32Kbit (128×256) SRAM，具有单端口6T位元宏。为了提高读性能，提出了一种带TRKBL旁路的RTW双泵CLK产生电路。采用双金属方案，提高了信号完整性和整体工作周期时间。在感应放大器中引入了局部联锁电路(LIC)，以降低有功功率并进一步提高Fmax。硅的实验结果表明，慢角晶圆可以达到4。24GHz, 1.0V/100°C, 5nm FinFET技术。

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A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology

A high speed IRIW two port 32Kbit (128×256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with TRKBL bypassing is proposed to enhance read performance. Double metal scheme is applied to improve signal integrity and overall operating cycle time. A Local Interlock Circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. The silicon results show that the slow corner wafer was able to achieve 4. 24GHz at 1.0V/100°C in 5nm FinFET technology.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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