Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications

Abstract

For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2\mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $\lt 5.9\%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $\lt 10.9\%$ for HPCs, to be cost-effective at similar IR drop.