SPIE Photomask Technology最新文献

{"title":"Parameter sensitive patterns for scatterometry monitoring","authors":"Jing Xue, Y. Ben, Chaohao Wang, Marshal A. Miller, C. Spanos, A. Neureuther","doi":"10.1117/12.746833","DOIUrl":"https://doi.org/10.1117/12.746833","url":null,"abstract":"This paper proposes a new highly sensitive scatterometry based Probe-Pattern Grating Focus Monitor. The high sensitivity is achieved by placing transparent lines spaced at the strong focus spillover distance of around 0.6λ/NA from the centerline of a 90 degree phase-shifted probe line that functions as an interferometer detector. The monitor translates the focus error into the probe line trench depth, which can be measured by scatterometry techniques. Simulations of optical imaging, resist development and Optical Digital Profilometry measurements are used to evaluate the expected practical performance. A linear model is developed to estimate focus error based on the measured probe trench depth. The results indicate that the ODP measurement from a single wafer focus setting can detect both the defocus direction and the defocus distance to well under 0.1 Rayleigh unit of defocus.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127029452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An approach of auto-fix post OPC hot spots","authors":"Ching-Heng Wang, Qingwei Liu, Liguo Zhang","doi":"10.1117/12.740406","DOIUrl":"https://doi.org/10.1117/12.740406","url":null,"abstract":"With the design rule shrinks rapidly, full chip robust Optical Proximity Correction (OPC) will definitely need longer time due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more difficult. For, the critical dimension of the design features is deeply sub exposure wavelength, and there is only limited room for the OPC correction. Usually very complicated fragment commands need to be developed to handle the shrinking designs, which can be infinitely complicated. So when you finished debug a sophisticated fragment scripts, you still cannot promise that the script is universal for all kinds of design. So when you find some hot spot after you apply OPC correction for certain design. The only thing you can do is to modify your fragmentation script and try to re-apply OPC on this design. But considering the increasing time that is needed for applying full chip OPC nowadays, re-apply OPC will definitely prolong the tape-out time. We here demonstrate an approach, through which we can automatically fix some simple hotspots like pinch, bridging. And re-run OPC for the full chip is not necessary now. However, this work is only the early study of the auto-fix of post OPC hot spots. There is still a long way need to go to provide a perfect solution of this issue.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129174423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"OPC development in action for advanced technology nodes","authors":"A. Wang, M. Fujimoto, P. V. van Adrichem, I. Bork, H. Yamashita","doi":"10.1117/12.746838","DOIUrl":"https://doi.org/10.1117/12.746838","url":null,"abstract":"In leading edge technologies, Optical Proximity Correction (OPC) plays a critical role in the total imaging flow. Large investments in terms of time and engineering resources are made to obtain the required models and recipes to get the OPC job done. In the model building area, the metrology component is becoming more and more critical. Questions like which structures to put in a calibration pattern, how to measure, where to measure them, and how often has a serious impact on the calibration dataset, and thus on the final model. Corner rounding starts to become an increasingly important factor in imaging and device performance. Because of this, the model 2D behavior needs to be verified as the least, using reliable metric. In this paper two techniques are described. Finally the cost of model building is discussed. When the number of measurements for a model calibration is considered, available machine time almost always plays a key role. In this paper, a slightly different approach is made on this problem by looking at the cost of the different components of model calibration, and how that is going to progress in the process generations to come.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117095681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving hyper-NA OPC using targeted measurements for model parameter extraction","authors":"B. Ward","doi":"10.1117/12.746576","DOIUrl":"https://doi.org/10.1117/12.746576","url":null,"abstract":"An alternative method of OPC model fitting based on model parameter sensitivity is presented. Theoretical advantages are discussed, including improved model quality and time to results. The parameter sensitivity method is applied using a basic optical model to 32nm logic node experimental data. Results include standard and parameter sensitivity model fits using both constant and variable threshold models. The results show that the parameter sensitivity methodology enables an overall model fit that is more physically-predictive than a standard OPC model fit.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115225703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells","authors":"Kuang-Kuo Lin, B. Wong, F. Driessen, E. Morita, S. Klaver","doi":"10.1117/12.747021","DOIUrl":"https://doi.org/10.1117/12.747021","url":null,"abstract":"DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122944045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Layout verification in the era of process uncertainty: requirements for speed, accuracy, and process portability","authors":"J. A. Torres, Ioana Graur, Mark Simmons, Suniti Kanodia","doi":"10.1117/12.746700","DOIUrl":"https://doi.org/10.1117/12.746700","url":null,"abstract":"A few years ago, model-based layout verification was used primarily with mask data preparation as a safety net to predict and avoid limited printability performance prior to mask fabrication. If certain layout locations would transfer poorly onto the wafer, the mask data was intercepted, preventing yield loss associated with \"mask issues.\" Such mask-related issues come primarily from three sources: Mask manufacture bias, OPC limitations and intrinsic layout configurations. While mask manufacture bias and OPC limitations can be addressed during the final stages of mask synthesis and manufacture, layout configurations that exhibit poor lithographic performance for a given process cannot be modified without considering the electrical effect such new topologies will induce in the modified layout. In principle, marginally performing layouts can be removed from the design by adequately interpreting geometric design rules. Unfortunately, while such rules are strictly defined for 1D, they are not as well-defined for arbitrary 2D configurations. For that reason, several approaches to transferring sufficient process information to the layout synthesis tools to prevent the presence of layout configurations incompatible with the production process have been attempted. However, when the production process is not fully developed, using these approaches can potentially limit the portability of the layout. In this paper, we describe and evaluate different approaches to defining reasonable layout verification targets by exploring various methods to reduce verification time, maintain accuracy and improve layout portability. First, to reduce verification time, we implement a method to quickly scan the layout for large variations without the need to run the actual OPC recipe. This paper describes the characteristics of a model that defines a pseudo-OPC process. Next, because the pseudo-OPC process cannot be mapped exactly to the real OPC process, there are accuracy limitations when using only the pseudo-OPC process. To overcome these limitations, the verification system follows an incremental approach, in which those regions previously selected are evaluated with the full mask synthesis recipe to reduce the number of falsely detected errors. Finally, to investigate the issue of portability, we evaluate how different errors evolve with maturing process and OPC recipe conditions for different layout patterns.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124574259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2D measurement using CD SEM for arbitrarily shaped patterns","authors":"Hyung-Joo Lee, So-Yoon Bae, Dong-Hoon Chung, S. Woo, Hanku Cho, J. Matsumoto, Takayuki Nakamura, Dong Il Shin, Taejun Kim","doi":"10.1117/12.746453","DOIUrl":"https://doi.org/10.1117/12.746453","url":null,"abstract":"As the design rule of lithography becomes smaller, accuracy and precision in Critical Dimension (CD) and controllability of pattern-shape are required in semiconductor production. Critical Dimension Scanning Electron Microscope (CD SEM) is an essential tool to confirm the quality of the mask such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in the case of extremely rounded region of arbitrary enclosed patterns, CD fluctuation depending on Region of Interest (ROI) is very serious problem in Mask CD control, so that it decreases the yield. In order to overcome this situation, we have been developing 2-dimensonal (2D) method with system makers and comparing CD performance between mask and wafer using enclosed arbitrary patterns. In this paper, we summarized the results of our evaluation that compare error budget between 1-dimensonal (1D) and 2D data using CD SEM and other optical metrology systems.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130096204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Preliminary verifiability of the aerial image measurement tool over photolithography process","authors":"Hyemi Lee, Goomin Jeong, Sangchul Kim, O. Han","doi":"10.1117/12.746786","DOIUrl":"https://doi.org/10.1117/12.746786","url":null,"abstract":"The AIMS (Aerial Image Measurement Tool) measures approximate aerial images to scanner results by adjusting the numerical aperture, illumination type and partial parameters. Accordingly, AIMS tool is used generally to verify the issue points during manufacturing a mask. Normally using a mask for photolithography needs twice verifications. One is the qualification in the mask shop. The other is verification over the photo process using the mask in the wafer fab. If evaluated data at AIMS can be trusted about photo process ability including energy latitude (EL), depth of focus (DOF), CD uniformity (CDU), pattern fidelity and mask defects including repair area, AIMS can function as a first filter before shipping the mask. That means the AIMS data can be used as a preliminary data in the wafer fab. So this study is focused on correlation between measured data at AIMS fab 193i and ArF scanner over the photo process such as EL, DOF, CDU, pattern fidelity and mask defects. First, various patterns are made on attenuated PSM from 80 to 65nm tech. Next correlations are calculated about EL, DOF and CDU by using same optical conditions, measurement points and etc at AIMS and Scanner. Also the aerial images from AIMS are compared with scanner results on defective side how those are matched with each other. Consequently defect printability and CDU map at AIMS were similar to the scanner. In CDU point of view, AIMS exceeds the predictive ability of the mask CD SEM. Moreover it means that wafer CDU can be corrected (improved) independently on the CDU result of the wafer fab by using CDU correctable femto laser tool which reduces transmittance of the mask. Surprisingly, it is possible. And Aerial image about mask defects including repair area is useful to predict the problem of the mask, since it is similar to wafer results. But aerial image compared with wafer image has more difference at 65nm technology node than at 80nm. If adjustment of threshold or measuring method can be done, prediction of the scanner result will have no matter. In conclusion, predictive results at AIMS over photo process can be applied as a preliminary data and it can be used to another index verifying the mask quality.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"6730 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring the sources of MEEF in contact SRAMs","authors":"E. Gallagher, I. Stobert, M. Higuchi, D. Samuels","doi":"10.1117/12.746801","DOIUrl":"https://doi.org/10.1117/12.746801","url":null,"abstract":"Optical Proximity Correction (OPC) relies on predictive modeling to achieve consistent wafer results. To that end, understanding all sources of variation is essential to the successful implementation of OPC. This paper focuses on challenging SRAM layouts of contacts to study the sources of wafer variation. A range of shape geometries and contact configurations are studied. Contact shapes are no longer restricted to simple rectangles on the mask, some more complex OPC outputs may include shapes like H's or T's or even more fragmented figures. The result is a large group of parameters that can be measured at both mask and wafer level. The dependence of mask variation on geometry is studied through the statistical distributions of parameter variations. The mask metrology output is expanded from traditional linear dimensional measurements to include area, line edge roughness, corner rounding, and shape-to-shape metrics. Wafer mask error enhancement factor (MEEF) is then calculated for the various contact geometries. This collection of data makes it possible to study variation on many levels and determine the underlying source of wafer variations so that, ultimately, they can be minimized.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129550471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast three-dimensional simulation of buried EUV mask defect interaction with absorber features","authors":"C. Clifford, A. Neureuther","doi":"10.1117/12.746486","DOIUrl":"https://doi.org/10.1117/12.746486","url":null,"abstract":"To simulate the interaction of buried defects and absorber features in EUV masks, a full three-dimensional, fast, integrated, simulator based on ray tracing and a thin mask model is presented. This simulator allows rapid assessment of the effects of buried defects on EUV printing. This new simulator, RADICAL (Rapid Absorber Defect Interaction Computation for Advanced Lithography), gives a 450X speed increase compared to FDTD, and matches FDTD within 1.5nm for predicting CD change due to a buried defect. RADICAL consists of three sequential steps: the propagation of the mask illumination down through the absorber pattern, the reflection off the defective multilayer, and the propagation back up through the absorber. A propagated thin mask model is used to model the down/up propagation through the absorber pattern and a ray tracing simulator is used for the multilayer reflection. These simulators are linked together using a Fourier transform to convert the near field output of one simulator step into a set of plane wave inputs for the next.","PeriodicalId":308777,"journal":{"name":"SPIE Photomask Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114717842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}