工艺不确定时代的布局验证:对速度、准确性和工艺可移植性的要求

J. A. Torres, Ioana Graur, Mark Simmons, Suniti Kanodia
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引用次数: 3

摘要

几年前,基于模型的布局验证主要用于掩模数据准备,作为安全网,在掩模制造之前预测和避免有限的印刷性能。如果某些布局位置传输到晶圆上的效果不佳,则可以拦截掩模数据,从而防止与“掩模问题”相关的产量损失。这些与掩模相关的问题主要来自三个方面:掩模制造偏差、OPC限制和内在布局配置。虽然掩模制造偏置和OPC限制可以在掩模合成和制造的最后阶段得到解决,但在给定工艺中表现出较差光刻性能的布局配置不能在不考虑这种新拓扑将在修改后的布局中引起的电效应的情况下进行修改。原则上,通过充分解释几何设计规则,可以从设计中删除次要的布局。不幸的是,虽然这些规则对一维是严格定义的,但对任意二维配置却没有这样的定义。由于这个原因,已经尝试了几种方法来将足够的工艺信息传递给布局合成工具,以防止与生产过程不兼容的布局配置的存在。然而,当生产过程没有完全开发时,使用这些方法可能会限制布局的可移植性。本文通过探索各种方法来描述和评估定义合理布局验证目标的不同方法,以减少验证时间,保持准确性和提高布局可移植性。首先,为了减少验证时间,我们实现了一种方法来快速扫描布局的大变化,而不需要运行实际的OPC配方。本文描述了一个定义伪opc进程的模型的特点。其次,由于伪OPC进程不能准确地映射到真实的OPC进程,因此仅使用伪OPC进程时存在精度限制。为了克服这些限制,验证系统采用增量方法,其中使用全掩膜合成配方对先前选择的区域进行评估,以减少误检测错误的数量。最后,为了研究可移植性问题,我们评估了不同布局模式下,不同的OPC配方条件和成熟过程对错误的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Layout verification in the era of process uncertainty: requirements for speed, accuracy, and process portability
A few years ago, model-based layout verification was used primarily with mask data preparation as a safety net to predict and avoid limited printability performance prior to mask fabrication. If certain layout locations would transfer poorly onto the wafer, the mask data was intercepted, preventing yield loss associated with "mask issues." Such mask-related issues come primarily from three sources: Mask manufacture bias, OPC limitations and intrinsic layout configurations. While mask manufacture bias and OPC limitations can be addressed during the final stages of mask synthesis and manufacture, layout configurations that exhibit poor lithographic performance for a given process cannot be modified without considering the electrical effect such new topologies will induce in the modified layout. In principle, marginally performing layouts can be removed from the design by adequately interpreting geometric design rules. Unfortunately, while such rules are strictly defined for 1D, they are not as well-defined for arbitrary 2D configurations. For that reason, several approaches to transferring sufficient process information to the layout synthesis tools to prevent the presence of layout configurations incompatible with the production process have been attempted. However, when the production process is not fully developed, using these approaches can potentially limit the portability of the layout. In this paper, we describe and evaluate different approaches to defining reasonable layout verification targets by exploring various methods to reduce verification time, maintain accuracy and improve layout portability. First, to reduce verification time, we implement a method to quickly scan the layout for large variations without the need to run the actual OPC recipe. This paper describes the characteristics of a model that defines a pseudo-OPC process. Next, because the pseudo-OPC process cannot be mapped exactly to the real OPC process, there are accuracy limitations when using only the pseudo-OPC process. To overcome these limitations, the verification system follows an incremental approach, in which those regions previously selected are evaluated with the full mask synthesis recipe to reduce the number of falsely detected errors. Finally, to investigate the issue of portability, we evaluate how different errors evolve with maturing process and OPC recipe conditions for different layout patterns.
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