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Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.最新文献

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Evaluation of BN-delta-doped multilayer reference materials for shallow depth profiling in SIMS 在SIMS中浅深度剖面中bn - δ掺杂多层参考材料的评价
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 2004-06-15 DOI: 10.1109/IWJT.2002.1225199
S. Yoshikawa, F. Toujou, Y. Homma, H. Takenaka, S. Hayashi, M. Inoue, K. Goto, R. Shimizu
{"title":"Evaluation of BN-delta-doped multilayer reference materials for shallow depth profiling in SIMS","authors":"S. Yoshikawa, F. Toujou, Y. Homma, H. Takenaka, S. Hayashi, M. Inoue, K. Goto, R. Shimizu","doi":"10.1109/IWJT.2002.1225199","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225199","url":null,"abstract":"We are developing multilayer reference materials for shallow depth profiling in secondary ion mass spectrometry (SIMS). In this report, the potential of boron-nitride (BN)/silicon (Si) multilayers as the reference materials for shallow depth profiling is shown from the standpoint of SIMS analyses.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Detailed modeling of source/drain parasitics and their impact on MOSFETs scaling 源/漏寄生的详细建模及其对mosfet缩放的影响
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225186
Seong-Dong Kim, J. Woo
{"title":"Detailed modeling of source/drain parasitics and their impact on MOSFETs scaling","authors":"Seong-Dong Kim, J. Woo","doi":"10.1109/IWJT.2002.1225186","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225186","url":null,"abstract":"The resistance components and key device/process parameters contributing of source/drain (S/D) parasitic resistance are investigated through advanced modeling for 50 nm gate-length MOSFET design and scaling. The silicide-diffusion contact resistance component is expected to be a major component in highly scaled nanometer MOS transistors. The key factors impact on MOSFET scaling are quantitatively examined based on 53 nm gate-length technology and the strategies for S/D engineering surmounting the scaling barriers associated with S/D parasitics are discussed.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"25 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TCAD simulation in development and fabrication of deep-sub-/spl mu/m devices 深亚/spl μ m器件开发与制造中的TCAD仿真
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225210
A. Erlebach, C. Zechner, A. Al-Bayati
{"title":"TCAD simulation in development and fabrication of deep-sub-/spl mu/m devices","authors":"A. Erlebach, C. Zechner, A. Al-Bayati","doi":"10.1109/IWJT.2002.1225210","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225210","url":null,"abstract":"In this paper experiences in use and application of TCAD in fabrication environment of deep sub-/spl mu/m semiconductor devices is given. Thereby we do not limit ourselves to standard process and device simulation but we discuss also the extension to parameter extraction, ESD and SER simulations. The main goal is to show how one can get a benefit from TCAD and what should be the expectation regarding accuracy and capability to predict. The limits of TCAD and the current status of 3D process and device simulation are discussed at the end of the paper.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129042148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of a small amount of oxygen during rapid thermal processing on cobalt salicide at 65 nm gate length 快速热加工中少量氧气对65 nm栅长水化钴的影响
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225208
Y. Kanda, M. Ogura, K. Honda, S. Tsutsumi, K. Maekawa, K. Kobayashi, M. Yoneda
{"title":"Influence of a small amount of oxygen during rapid thermal processing on cobalt salicide at 65 nm gate length","authors":"Y. Kanda, M. Ogura, K. Honda, S. Tsutsumi, K. Maekawa, K. Kobayashi, M. Yoneda","doi":"10.1109/IWJT.2002.1225208","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225208","url":null,"abstract":"The main issue in cobalt salicide process is the difficulty of obtaining low sheet resistances at narrow line width. In the present work, we have studied the relationship between oxygen concentration in rapid thermal processing (RTP) chamber and the electrical properties of cobalt silicide in CMOS devices. It is found that failures of CoSi/sub 2//poly-Si gate electrodes with 62 nm gate length are induced by a small amount of oxygen (25 ppm) in the chamber of RTP system.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Formation of low-resistive ultra-shallow n+/p junction by heat-assisted excimer laser annealing 热辅助准分子激光退火制备低阻超浅n+/p结
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225194
K. Kurobe, Y. Ishikawa, K. Kagawa, Y. Niwatsukino, A. Matusno, K. Shibahara
{"title":"Formation of low-resistive ultra-shallow n+/p junction by heat-assisted excimer laser annealing","authors":"K. Kurobe, Y. Ishikawa, K. Kagawa, Y. Niwatsukino, A. Matusno, K. Shibahara","doi":"10.1109/IWJT.2002.1225194","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225194","url":null,"abstract":"Low-resistive ultra-shallow n/sup +//p junctions were formed with Sb by a heat-assisted laser annealing method. A wide process window for laser energy density and heating temperature was obtained. Under that condition, Sb diffusion was small and did not affect junction depth. The obtained sheet resistance was about 540/spl Omega///spl square/ for junction depth of 21 nm.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124447847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SOI technology for future SoC 面向未来SoC的SOI技术
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225217
Y. Inoue
{"title":"SOI technology for future SoC","authors":"Y. Inoue","doi":"10.1109/IWJT.2002.1225217","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225217","url":null,"abstract":"SOI CMOS devices have been investigated for a long time and as the quality of SOI wafers has been improved as the same level of bulk-Si wafers and improvement of the speed performance of CMOS devices is becoming difficult, they have entered the phase of practical use. There are two approaches for the usage of SOI CMOS. One approach is the SOI CMOS in floating-body structure and the other is the one in body-tied structure. In the case of body-tied structure it is possible to realize the layout with the bulk-Si compatibility and to suppress the history effect due to the floating body structure. To keep the compatibility of bulk-Si CMOS technology, we developed the hybrid trench technology, which realizes the body-tied structure for each transistor and full isolation between NMOS and PMOS transistors.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121566739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Elevated source/drain engineering with smooth surface morphology for ultrathin-SOI CMOS 超薄soi CMOS表面光滑的高架源/漏工程
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225202
K. Sugihara, T. Nakahata, T. Matsumoto, S. Maeda, S. Maegawa, K. Ota, H. Sayama, H. Oda, T. Eimori, Y. Abe, T. Ozeki, Y. Inoue
{"title":"Elevated source/drain engineering with smooth surface morphology for ultrathin-SOI CMOS","authors":"K. Sugihara, T. Nakahata, T. Matsumoto, S. Maeda, S. Maegawa, K. Ota, H. Sayama, H. Oda, T. Eimori, Y. Abe, T. Ozeki, Y. Inoue","doi":"10.1109/IWJT.2002.1225202","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225202","url":null,"abstract":"A novel selective epitaxial growth (SEG) technology which combines low-temperature UHV-CVD and low-damage sidewall etch-back with a Cl/sub 2/-plasma is experimentally demonstrated for elevated S/D ultra-thin SOI CMOS devices. It is found that the deviation of the parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI FETs can be nearly as low as that in bulk FETs because the excellent epi-Si surface morphology enables a uniform CoSi/sub 2/ film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results mean that this SEG technology is promising for elevated S/D ultra-thin SOI CMOS devices for the 90-nm technology node and beyond.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131568915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nanocleaving: an enabling technology for ultra-thin SOI 纳米离层:超薄SOI的使能技术
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225214
M. Current
{"title":"Nanocleaving: an enabling technology for ultra-thin SOI","authors":"M. Current","doi":"10.1109/IWJT.2002.1225214","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225214","url":null,"abstract":"The principal features of CMOS transistor scaling into the SOI-era and the key steps of the Silicon Genesis SOI wafer fabrication technologies are outlined. Results for ultra-thin SOI wafers, with near and sub-Angstrom surface roughness over lateral scales up to 10 /spl mu/m and device layer thickness uniformity range (max-min) of /spl sim/5%, are presented for 200 and 300 mm SOI wafers. Some of the implications of SOI-CMOS scaling for ion implantation doping and SOI wafer fabrication are considered.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132182365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Suppression of migration during low pressure annealing for selective epitaxial growth on ultra-thin SOI 超薄SOI表面选择性外延生长低压退火过程中的迁移抑制
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225205
I. Mizushima, T. Sato, K. Miyano, Y. Tsunashima
{"title":"Suppression of migration during low pressure annealing for selective epitaxial growth on ultra-thin SOI","authors":"I. Mizushima, T. Sato, K. Miyano, Y. Tsunashima","doi":"10.1109/IWJT.2002.1225205","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225205","url":null,"abstract":"The paper deals about suppression of migration during low pressure annealing for selective epitaxial growth on ultra-thin SOI. The novel process sequence was proposed that satisfies both the suppression of the migration and the removal of native oxide by controlling the pressure and the temperature of hydrogen annealing. The proposed process was successfully applied for the formation of elevated source and drain structure fabricated on ultra-thin SOI wafer.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature activation of ion implanted dopants: a review 离子注入掺杂剂低温活化研究进展
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI: 10.1109/IWJT.2002.1225211
J. Borland
{"title":"Low temperature activation of ion implanted dopants: a review","authors":"J. Borland","doi":"10.1109/IWJT.2002.1225211","DOIUrl":"https://doi.org/10.1109/IWJT.2002.1225211","url":null,"abstract":"Ion implanted dopants can be electrically activated through low temperature annealing in the 450/spl deg/C to 800/spl deg/C as reported in literature over the past 25 years. However, researchers in the last few years have applied this technique to realize ultra shallow junctions (USJ) for source drain extensions to satisfy the device junction roadmap requirements for the 65 nm node and beyond. Therefore this paper will review the current status of low temperature annealing for USJ formation.","PeriodicalId":300554,"journal":{"name":"Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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