Nanocleaving: an enabling technology for ultra-thin SOI

Abstract

The principal features of CMOS transistor scaling into the SOI-era and the key steps of the Silicon Genesis SOI wafer fabrication technologies are outlined. Results for ultra-thin SOI wafers, with near and sub-Angstrom surface roughness over lateral scales up to 10 /spl mu/m and device layer thickness uniformity range (max-min) of /spl sim/5%, are presented for 200 and 300 mm SOI wafers. Some of the implications of SOI-CMOS scaling for ion implantation doping and SOI wafer fabrication are considered.