纳米离层:超薄SOI的使能技术

Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Pub Date : 1900-01-01 DOI:10.1109/IWJT.2002.1225214

M. Current

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引用次数: 3

摘要

概述了CMOS晶体管进入SOI时代的主要特征和硅创世纪SOI晶圆制造技术的关键步骤。超薄SOI晶圆的结果表明，在200和300 mm SOI晶圆的横向尺度上，近埃和亚埃表面粗糙度高达10 /spl μ m/ m，器件层厚度均匀性范围(最大-最小)为/spl μ m/5%。本文讨论了SOI- cmos标度对离子注入掺杂和SOI晶圆制造的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Nanocleaving: an enabling technology for ultra-thin SOI

The principal features of CMOS transistor scaling into the SOI-era and the key steps of the Silicon Genesis SOI wafer fabrication technologies are outlined. Results for ultra-thin SOI wafers, with near and sub-Angstrom surface roughness over lateral scales up to 10 /spl mu/m and device layer thickness uniformity range (max-min) of /spl sim/5%, are presented for 200 and 300 mm SOI wafers. Some of the implications of SOI-CMOS scaling for ion implantation doping and SOI wafer fabrication are considered.

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Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.

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