Detailed modeling of source/drain parasitics and their impact on MOSFETs scaling

Abstract

The resistance components and key device/process parameters contributing of source/drain (S/D) parasitic resistance are investigated through advanced modeling for 50 nm gate-length MOSFET design and scaling. The silicide-diffusion contact resistance component is expected to be a major component in highly scaled nanometer MOS transistors. The key factors impact on MOSFET scaling are quantitatively examined based on 53 nm gate-length technology and the strategies for S/D engineering surmounting the scaling barriers associated with S/D parasitics are discussed.