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2004 IEEE Workshop on Microelectronics and Electron Devices最新文献

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Electrical characterization of through-wafer interconnects 晶圆互连的电学特性
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297363
T. E. Lawrence, S. M. Donovan, William B. Knowlton, J. Rush-Byers, Amy J. Moll
{"title":"Electrical characterization of through-wafer interconnects","authors":"T. E. Lawrence, S. M. Donovan, William B. Knowlton, J. Rush-Byers, Amy J. Moll","doi":"10.1109/WMED.2004.1297363","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297363","url":null,"abstract":"Through-wafer interconnects (TWI) allows 3-D chip stacking enabling integration of multiple chip functions (i.e. opto-electronic, analog or digital) with reduced power and space requirements. To date, non-destructive characterization techniques for determining interconnect integrity and reliability have not been developed. This work examines a specially modified electrical four-point probe for non-destructive characterization of TWI's. Technical challenges and measurement optimization methods are reported.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126503201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Adjusting poly texture to reduce TiSi/sub 2/ agglomeration [semiconductor manufacturing] 调整多晶织构减少TiSi/ sub2 /团聚[半导体制造]
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297361
Jingyan Zhang, Q. Pan
{"title":"Adjusting poly texture to reduce TiSi/sub 2/ agglomeration [semiconductor manufacturing]","authors":"Jingyan Zhang, Q. Pan","doi":"10.1109/WMED.2004.1297361","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297361","url":null,"abstract":"With its low resistivity and relatively high thermal stability, TiSi/sub 2/ is a promising gate material for use in semiconductor manufacturing. It can survive the oxidization and backend thermal steps without a spacer; however, it sometimes agglomerates into the gate poly. This paper outlines a possible solution that entails replacing the normal amorphous gate poly with a different type of as-deposited poly to reduce the gate short caused by agglomeration. Scanning electron microscopy (SEM) inspections of cross sections of blank test wafers reveal the potential of this method.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114161395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of jitter in clock distribution networks 时钟分配网络抖动分析
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297348
R. Darapu, C.W. Zhang, L. Forbes
{"title":"Analysis of jitter in clock distribution networks","authors":"R. Darapu, C.W. Zhang, L. Forbes","doi":"10.1109/WMED.2004.1297348","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297348","url":null,"abstract":"A technique for the simulation of jitter in clock distribution networks will be demonstrated. Noise is injected as a time domain signal into each driver stage in the clock distribution network and large signal non-linear transient simulations are performed to obtain the distribution of clock periods and the subsequent jitter in the clock signal. In the simplest case the noise is the thermal channel noise of the CMOS driver transistors, and the results can be compared to the simple analytical estimate given by Gray et al.[1994]. It will be shown that there is a good agreement between the simulation results and analytical estimates if a modified analytical formula is used where the simple estimate for delay by Gray et al. is replaced by the observed delay from simulations. The technique can be extended and is directly applicable to other types of noise such as power supply noise.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124065661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
MOSFET 1/f noise measurement under switched bias conditions 开关偏置条件下MOSFET 1/f噪声测量
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297357
C.W. Zhang, M. Y. Louie, L. Forbes
{"title":"MOSFET 1/f noise measurement under switched bias conditions","authors":"C.W. Zhang, M. Y. Louie, L. Forbes","doi":"10.1109/WMED.2004.1297357","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297357","url":null,"abstract":"Klumperink et al, have recently had a number of publications on the low frequency noise of MOSFETs under switched gate bias conditions. Since this is an important consideration in the low frequency noise in analog circuits with switching, we have investigated the signal processing technique used in some detail with respect to the data presented in the IEEE Electron Device Letters (vol.2, no.1, p. 43-46, 2000). No consideration was given to phase noise, a mixing with and modulation of the switched bias drain current by 1/f noise, in the analysis of the data. This can result in a response on the spectrum analyzer which corresponds very closely to the experimental data where the switched bias off gate voltage is near the threshold voltage. At low frequencies there will be just 1/f noise, then a plateau caused by the sum of 1/f noise and phase noise, a peak corresponding to the fundamental component of the switched bias, and at higher frequencies a phase noise in excess of the 1/f noise.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 /spl mu/m TSMC CMOS 2.4 GHz高增益低功耗窄带低噪声放大器(LNA)，采用0.18 /spl mu/m TSMC CMOS
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297350
E. Kunz, S. Parke
{"title":"2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 /spl mu/m TSMC CMOS","authors":"E. Kunz, S. Parke","doi":"10.1109/WMED.2004.1297350","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297350","url":null,"abstract":"A 2.4 GHz low-noise amplifier has been designed in a standard CMOS 0.18 TSMC process. The measured noise factor and gain are 1.65dB and 51dB, respectively, at 2.4 GHz. The LNA draws 1.75 mA from a 1.8 V supply voltage. The detailed design process and simulations are detailed in this paper.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121234830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Leakage power reduction using self-bias transistor in VLSI circuits [digital circuits] 自偏置晶体管在VLSI电路中的泄漏功率降低[数字电路]
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297355
H. Gopalakrishnan, Wen-Tsong Shiue
{"title":"Leakage power reduction using self-bias transistor in VLSI circuits [digital circuits]","authors":"H. Gopalakrishnan, Wen-Tsong Shiue","doi":"10.1109/WMED.2004.1297355","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297355","url":null,"abstract":"Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties 作为晶圆碰撞结构的焊料-钝化连接的评估:1 .绝缘性能
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297364
I. R. Harvey, M. Larsen, D. Turner, I. Doyle, J. Somers, J. Ortowski
{"title":"Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties","authors":"I. R. Harvey, M. Larsen, D. Turner, I. Doyle, J. Somers, J. Ortowski","doi":"10.1109/WMED.2004.1297364","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297364","url":null,"abstract":"This paper describes the concept of direct mechanical attachment of a solder bump to the base IC passivation, in what has been called \"wide via\" design - a low-cost design option rejected for use by Bourns. In general use over an ASIC or other active device, this architecture relies upon the oxide/nitride passivation stack for complete conformal coverage of IC routing metalization, and assumes an absence of pinholes. We have created a test chip to evaluate the validity of these assumptions under BHT testing, as well as to enable comparative thermomechanical performance and induced parasitic effects. In this paper, we describe the BHT and failure analysis results indicating that passivation processes need to be optimized in order for this architecture to work. This result has implications in \"over-the-fence\" design in which a bump supplier makes assumptions regarding the quality of passivation from an IC manufacturer, and how passivation stacks which were good enough for peripheral wire bonding applications may need to be re-thought for area-array bumping.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Process development of electron beam lithography in an academic environment 电子束光刻工艺在学术环境下的发展
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297370
G.S. Gatlin, C. Eskridge, J. Brinkerhoff, J. Fife, J. Jessing
{"title":"Process development of electron beam lithography in an academic environment","authors":"G.S. Gatlin, C. Eskridge, J. Brinkerhoff, J. Fife, J. Jessing","doi":"10.1109/WMED.2004.1297370","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297370","url":null,"abstract":"This paper compares the processes of photolithography and electron beam lithography (EBL). In addition, we discuss the procedure used to implement EBL in a university laboratory, specifically Boise State University's (BSU) Idaho Microfabrication Laboratory (IML).","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Packaging effect on reliability of Cu/low k interconnects 封装对铜/低钾互连可靠性的影响
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297342
Guotao Wang, P. Ho, S. Groothuis
{"title":"Packaging effect on reliability of Cu/low k interconnects","authors":"Guotao Wang, P. Ho, S. Groothuis","doi":"10.1109/WMED.2004.1297342","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297342","url":null,"abstract":"In a plastic flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results to investigate the chip-package interaction and its impact on low k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low k interfaces. Then results from 3D FEA, based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry, to investigate the chip-package interaction for SiLK and MSQ low k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"52 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120993579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Scaling trends in DRAM technology DRAM技术的扩展趋势
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297339
G. Bronner
{"title":"Scaling trends in DRAM technology","authors":"G. Bronner","doi":"10.1109/WMED.2004.1297339","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297339","url":null,"abstract":"Summary form only given. Trends in scaling DRAM to 0.11 /spl mu/m and below are reviewed. Scaling techniques used in earlier generations for the array access transistor and the storage capacitor are running into limitations, necessitating changes in electrical operating mode, cell structure, and processing innovations. Although a variety of options exist for advancing the technology, including low-voltage operation, non-planar array transistor MOSFETs, and novel capacitor structures and materials, uncertainties exist over the which of these will prove workable in manufacturing. This paper discusses the interrelationships among the DRAM scaling requirements and solutions.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121445247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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