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2004 IEEE Workshop on Microelectronics and Electron Devices最新文献

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A statistical model based ASIC skew selection method 一种基于统计模型的ASIC偏度选择方法
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297353
D.T. Wang, W. Mcnall
{"title":"A statistical model based ASIC skew selection method","authors":"D.T. Wang, W. Mcnall","doi":"10.1109/WMED.2004.1297353","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297353","url":null,"abstract":"Cross wafer speed variations in the 0.13 /spl mu/m process and beyond are significant enough to be considered in ASIC skew selection. Traditional Idsat and Vt measurements on a few sites of the wafer to gauge wafer speed simply does not work. Multiple skew lot runs to get proper skew wafers is financially prohibitive and part skew uncertainty makes it impossible to qualify product with a reasonable number of skew parts. Typical design practice for high-speed ASICs is to add a PVT monitor on the die. For area critical applications, scribe PVT monitors can be used. The PVT circuitry can be as simple as an inverter ring oscillator chain. We present a methodology based on on-chip or on-scribe ring oscillator data to bin the ASIC skew parts. Statistical modeling, PVT monitor sensitivity and actual experiment data are discussed. Based on the proposed methodology, proper skew parts can be selected for product testing so that products are validated cross all process corners.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"71 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113964203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Comparing rapid thermal process and low-temperature furnace annealed poly test wafers by SIMS and FTIR 利用SIMS和FTIR对快速热处理和低温炉退火的多晶片进行了比较
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297368
Jingyan Zhang, J. Mathew, M. Canavan, W. Morinville
{"title":"Comparing rapid thermal process and low-temperature furnace annealed poly test wafers by SIMS and FTIR","authors":"Jingyan Zhang, J. Mathew, M. Canavan, W. Morinville","doi":"10.1109/WMED.2004.1297368","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297368","url":null,"abstract":"As the poly deposition process monitor, poly test wafers (TWS) run with production wafers are generally annealed using the rapid thermal process (RTP) to achieve fast, stable results. But real production wafers often receive an extended, low-temperature furnace thermal process after poly deposition. For this reason, there is always a question about whether or not RTP effectively simulates the thermal budget the device wafers receive during the whole process. During this study, the same processed poly films, both n-type and p-type, go through the RTP furnace for 8 hours at 600/spl deg/C. Comparing the secondary ion mass spectrometry (SIMS) profile and Fourier transform infrared spectroscopy (FTIR) of the Si-H bond led us to question whether the RTP process is reliable enough to be used as the poly deposition process monitor.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127496632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pattern alignment effects in through-wafer bulk micromachining of (100) silicon (100)硅晶圆体微加工中的模式对准效应
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297360
P. Reddy, J. Jessing
{"title":"Pattern alignment effects in through-wafer bulk micromachining of (100) silicon","authors":"P. Reddy, J. Jessing","doi":"10.1109/WMED.2004.1297360","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297360","url":null,"abstract":"Precise alignment of the mask patterns relative to wafer crystallographic orientation is critical in the fabrication of many MEMS devices. Slight misalignment between the two can create striations and other defects in the etched sidewalls using an orientation dependent etchant such as potassium hydroxide (KOH). This paper focuses on the characterization of the resultant geometries due to the deliberate misalignment of photolithographically defined patterns relative to the [110] plane in (100) orientation silicon. The surface roughness of the etched (111) sidewall are characterized using optical microscopy, scanning electron microscopy and profilometry.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130283472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Non-linear DAC implementations in DDFS DDFS中的非线性DAC实现
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297372
Zhihe Zhou, I. Horowitz, G. la Rue
{"title":"Non-linear DAC implementations in DDFS","authors":"Zhihe Zhou, I. Horowitz, G. la Rue","doi":"10.1109/WMED.2004.1297372","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297372","url":null,"abstract":"A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128354945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver 用于直接转换-零中频接收机的5.6 ghz CMOS双平衡次谐波混频器
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297374
P. Upadhyaya, M. Rajashekharaiah, D. Heo
{"title":"A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver","authors":"P. Upadhyaya, M. Rajashekharaiah, D. Heo","doi":"10.1109/WMED.2004.1297374","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297374","url":null,"abstract":"A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-/spl mu/m CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2/spl deg/ LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm/sup 2/ of silicon real estate.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127839990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
The future of silicon microelectronics 硅微电子的未来
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297335
S. Hillenius
{"title":"The future of silicon microelectronics","authors":"S. Hillenius","doi":"10.1109/WMED.2004.1297335","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297335","url":null,"abstract":"The silicon microelectronic industry has gone through exponential growth in applications, complexity, density, and cost of manufacturing over the last several decades. The challenges in device physics for scaling transistors as well as the design challenges and economic challenges are reviewed and described in the context of how these forces are shaping the way we do business.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126480267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Atomically controlled processing for future Si-based devices 未来硅基器件的自动控制处理
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297343
J. Murota, M. Sakuraba, S. Takehiro
{"title":"Atomically controlled processing for future Si-based devices","authors":"J. Murota, M. Sakuraba, S. Takehiro","doi":"10.1109/WMED.2004.1297343","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297343","url":null,"abstract":"One of the main requirements for Si-based ultrasmall devices is atomic-order control of process technology. Here we show the concept of atomically controlled processing, based on atomic-order surface reaction control. Self-limiting formation of 1-3 atomic layers of group IV or related atoms in the thermal adsorption and reaction of hydride gases (SiH/sub 4/, GeH/sub 4/, NH/sub 3/, PH/sub 3/, CH/sub 4/ and SiH/sub 3/CH/sub 3/) on Si(100) and Ge(100) are generalized, based on the Langmuir-type model. Si epitaxial growth over the N and P layer already-formed on the Si(100) surface is achieved. It is found that a higher level of electrical P atoms exist in such films, compared with doping under thermal equilibrium conditions. These results open the way to atomically controlled technology for ultralarge-scale integrations.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of hydrogen in passivation PECVD nitride film on DRAM refresh performance 钝化PECVD氮化膜中氢对DRAM刷新性能的影响
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297369
Z. Yin, D. Christianson, R. Pasta
{"title":"Effects of hydrogen in passivation PECVD nitride film on DRAM refresh performance","authors":"Z. Yin, D. Christianson, R. Pasta","doi":"10.1109/WMED.2004.1297369","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297369","url":null,"abstract":"It was found that passivation nitride significantly affects DRAM refresh performance. To determine the factors in the nitride film that contributed to improved refresh performance, several analyses, such as Fourier-transform infrared spectrum (FTIR), thermal desorption spectrum (TDS), and x-ray photon spectroscopy (XPS), were performed on plasma enhanced chemical vapor deposition (PECVD) nitride film. The data revealed that the film with high Si-H bond in PECVD nitride film release more hydrogen in subsequent thermal process, in turn, to improved refresh performance.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An asynchronous GALS interface with applications 与应用程序的异步GALS接口
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297347
S.F. Smith
{"title":"An asynchronous GALS interface with applications","authors":"S.F. Smith","doi":"10.1109/WMED.2004.1297347","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297347","url":null,"abstract":"A low-latency asynchronous interface for use in globally-asynchronous locally-synchronous (GALS) integrated circuits is presented. The interface is compact and does not alter the local clocks of the interfaced local clock domains in any way (unlike many existing GALS interfaces). Two applications of the interface to GALS systems are shown. The first is a single-chip shared-memory multiprocessor for generic supercomputing use. The second is an application-specific coprocessor for hardware acceleration of the Smith-Waterman algorithm. This is a bioinformatics algorithm used for sequence alignment (similarity searching) between DNA or amino acid (protein) sequences and sequence databases such as the recently completed human genome database.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun 一个紧凑的5.6 GHz低噪声放大器与新的片上增益可控有源平衡
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297375
M. Rajashekharaiah, P. Upadhyaya, D. Heo
{"title":"A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun","authors":"M. Rajashekharaiah, P. Upadhyaya, D. Heo","doi":"10.1109/WMED.2004.1297375","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297375","url":null,"abstract":"A dual gain low noise amplifier for a 5.6 GHz ISM band direct conversion receiver, has been designed using a TSMC 0.25 /spl mu/m CMOS process and features a gain controllable on-chip active balun. The LNA provides gains of 19.5 dB and 12 dB in the two modes with 50% power savings in the low gain mode, while a noise figure of 3.1 dB and an IIP3 of -11.5 dBm have been achieved. A simple and novel gain control technique has been adopted and the gain control circuitry has been integrated with the balun.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115609143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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