{"title":"A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver","authors":"P. Upadhyaya, M. Rajashekharaiah, D. Heo","doi":"10.1109/WMED.2004.1297374","DOIUrl":null,"url":null,"abstract":"A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-/spl mu/m CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2/spl deg/ LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm/sup 2/ of silicon real estate.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE Workshop on Microelectronics and Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMED.2004.1297374","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-/spl mu/m CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2/spl deg/ LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm/sup 2/ of silicon real estate.