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2004 IEEE Workshop on Microelectronics and Electron Devices最新文献

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A review of RF ESD protection design [RF IC applications] 射频ESD保护设计综述[射频集成电路应用]
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297340
A. Wang
{"title":"A review of RF ESD protection design [RF IC applications]","authors":"A. Wang","doi":"10.1109/WMED.2004.1297340","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297340","url":null,"abstract":"This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF ICs. ESD protection basics, key issues in RF ESD protection, design methods, RF ESD protection evaluation techniques and RF ESD protection solutions are discussed.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114348196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Beyond nanoscale DRAM and flash challenges and opportunities for research in emerging memory devices 超越纳米级DRAM和闪存对新兴存储设备研究的挑战和机遇
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-09-27 DOI: 10.1109/WMED.2004.1297344
L. Tran
{"title":"Beyond nanoscale DRAM and flash challenges and opportunities for research in emerging memory devices","authors":"L. Tran","doi":"10.1109/WMED.2004.1297344","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297344","url":null,"abstract":"As dynamic random access memory (DRAM) and flash nonvolatile memory (NVM) technologies are entering their 4/sup th/ decade of continuing growth and progress, difficulties in scaling these respective devices have surfaced both in processing and device miniaturization. This paper addresses these challenges and presents emerging device alternatives with their perspective challenges and opportunities for research and development in this field.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124264797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental investigation of bare silicon wafer warp 裸硅片翘曲的实验研究
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2004-04-16 DOI: 10.1109/WMED.2004.1297371
N. Draney, Jun Liu, T. Jiang
{"title":"Experimental investigation of bare silicon wafer warp","authors":"N. Draney, Jun Liu, T. Jiang","doi":"10.1109/WMED.2004.1297371","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297371","url":null,"abstract":"IC packaging trends demand smaller packaging, which translates to thinner silicon; in some cases as thin as 50 /spl mu/m. Thinning below 305 /spl mu/m induces significant warp in product/metal wafers, which continues to increases as wafers are thinned further. Increased wafer warp results in handling/processing issues. Studies have been performed on product/metal wafers to characterize warp. These studies have shown a linear relationship between wafer warp and 1/thickness¿2. Several factors, in combination, have been shown to contribute to warp in product/metal wafers such as: metal layers, polyimide layers, BCB layers, metal density, thermal stress, tilt direction, front side tension, backside tension, and gravity. The wafer warp phenomenon observed in product/metal wafers is also observed in bare silicon wafers. The difference between bare silicon test wafers and product wafers is the layering of the circuitry side on product/metal wafers, which has shown to be a large contributor to wafer warp. Damage to the wafer backside during conventional grinding can induce a large amount of warp in both product/metal and bare silicon wafers.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
CMOS technology for MS/RF SoC 用于MS/RF SoC的CMOS技术
2004 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2003-06-05 DOI: 10.1109/WMED.2004.1297341
C. H. Diaz
{"title":"CMOS technology for MS/RF SoC","authors":"C. H. Diaz","doi":"10.1109/WMED.2004.1297341","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297341","url":null,"abstract":"The development of short-range wireless communication has become exceedingly important due to the emerging market of WLAN and Bluetooth. CMOS technology has emerged as the top solution due to its cost advantage, performance improvement and ease of integration for high-performance digital circuits and high-speed analog/RF circuits. Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF SoC technology from a scaling perspective.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130487749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
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