CMOS technology for MS/RF SoC

Abstract

The development of short-range wireless communication has become exceedingly important due to the emerging market of WLAN and Bluetooth. CMOS technology has emerged as the top solution due to its cost advantage, performance improvement and ease of integration for high-performance digital circuits and high-speed analog/RF circuits. Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF SoC technology from a scaling perspective.