{"title":"Interaction effects of slurry chemistry on chemical mechanical planarization of electroplated copper","authors":"P. Miranda, J. A. Imonigie, A. Moll","doi":"10.1109/WMED.2004.1297359","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297359","url":null,"abstract":"Recent studies have been conducted investigating the effects of slurry chemistry on the copper CMP process. Slurry pH and hydrogen peroxide concentration are two important variables that must be carefully formulated in order to achieve desired removal rates and uniformity. In applications such as through-wafer vertical interconnects, slurry chemistry effects must be thoroughly understood when copper plating thicknesses can measure up to 20 /spl mu/m thick. The species of copper present on the surface of the wafer can be controlled through formulation of the slurry chemistry resulting in minimizing non-uniformity while aggressively removing copper. Using a design of experiments (DOE) approach, this study was performed, investigating the interaction between the two variables during CMP. Using statistical analysis techniques, a better understanding of the interaction behavior between the two variables and the effect on removal rate and uniformity is achieved.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"387 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114902819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of a micro-nozzle and ion mobility spectrometer in LTCC","authors":"D. Plumlee, J. Steciak, A. Moll","doi":"10.1109/WMED.2004.1297362","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297362","url":null,"abstract":"Multilayer ceramic packaging materials provide a versatile platform to fabricate a wide variety of devices from sensors to micro-nozzles. Our research is focused on developing robust sensors for underground deployment and monopropellant micro nozzles for satellite attitude adjustment applications. An LTCC monopropellant micro-nozzle is being developed and tested to provide small thrust vectors for satellite attitude adjustments. High purity hydrogen peroxide undergoes a strong exothermic decomposition reaction in the presence of a silver catalyst. A micro-nozzle and catalyst chamber has been designed to convert hydrogen peroxide liquid to functional thrust. The device uses internal fluidic channels to direct the propellant to a silver lined catalyst chamber. The catalyst decomposes the propellant into water vapor and oxygen at temperatures near 1029 K. The hot gases are then expelled through a contoured nozzle to provide thrust. Complex internal geometric features are created using a CNC milling machine. An ion mobility spectrometer (IMS) is being developed for permanent deployment below ground to continuously analyze groundwater pollutants. Each segment was constructed of multiple layers of green tape. Five Kovar inserts were embedded in the device to function as ion gates. Reduction in size, hermeticity and system integration was made possible by the novel use of LTCC packaging technology.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116745708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Howard E. Rhodes, G. Agranov, C. Hong, U. Boettiger, R. Mauritzson, John Ladd, I. Karasev, Jeff A. Mckee, E. Jenkins, W. Quinlin, Inna Patrick, Jian Li, Xiaofeng Fan, R. Panicacci, S. Smith, Chandra Mouli, J. Bruce
{"title":"CMOS imager technology shrinks and image performance","authors":"Howard E. Rhodes, G. Agranov, C. Hong, U. Boettiger, R. Mauritzson, John Ladd, I. Karasev, Jeff A. Mckee, E. Jenkins, W. Quinlin, Inna Patrick, Jian Li, Xiaofeng Fan, R. Panicacci, S. Smith, Chandra Mouli, J. Bruce","doi":"10.1109/WMED.2004.1297338","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297338","url":null,"abstract":"In this paper, we present a performance summary of CMOS imager pixels from 5.2 /spl mu/m to 4.2 /spl mu/m using 0.18 /spl mu/m imager design rules, then to 3.2 /spl mu/m using 0.15 /spl mu/m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based on technology shrinks of Micron's 2P3M imager process, and each of the technology nodes report excellent CMOS imager low-noise, high-sensitivity, low-lag, and low-light performance, matching that of state-of-the-art charged-coupled device (CCD) imagers. We have put a model in place to provide the predictive performance of smaller pixels, and then use that model to discuss performance expectations down to 2.0 /spl mu/m pixels. With the combination of imager design rules, pixel architecture, and process technology tailored for CMOS imagers, we see no fundamental reason that CMOS imagers should not be able to continue matching CCD performance as pixel sizes shrink.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Clock and data recovery circuits with fast acquisition and low jitter","authors":"Ruiyuan Zhang, G. la Rue","doi":"10.1109/WMED.2004.1297349","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297349","url":null,"abstract":"This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Fabricated in a 0.5 /spl mu/m CMOS process, the combined CDR achieves operation up to 750 Mbps. Measurements show at least a 6% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps at 688 Mbps after a PLL lock time of 700 ns. Power dissipation is 300 mW and die area is 1.4 /spl times/ 1.4 mm/sup 2/.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134164380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Metal-insulator-Si (MIS) structure for advanced DRAM cell capacitor","authors":"Lin Zheng, E. Ping","doi":"10.1109/WMED.2004.1297356","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297356","url":null,"abstract":"The conventional DRAM cell capacitor with silicon-insulator-silicon (SIS) structure limits the scaling of capacitor cell size because the depletion layer of the polycrystalline-Si electrode becomes more severe as the cell dielectrics (ONO) thickness reaches the sub-50 /spl Aring/ region. This paper demonstrates that capacitance can be significantly increased by using a metal-insulator-Si (MIS) structure where the top electrode is metal TiN and the bottom electrode is semi-hemisphere Si grain (HSG). Capacitance can be further enhanced with PH/sub 3//NH/sub 3/ anneal to the HSG. The effects of post high-temperature anneal on the stability of the MIS structure are also discussed.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132236767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Through wafer interconnects on active pMOS devices","authors":"V. Johnson, J. Jozwiak, A. Moll","doi":"10.1109/WMED.2004.1297358","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297358","url":null,"abstract":"The objective of this research is to demonstrate the ability to create through-wafer interconnects (TWIs) on wafers with active devices. TWIs have previously been demonstrated on blank Si wafers. The application of TWIs in an industrial setting requires no damage or yield loss to the existing devices during additional processing steps. The test vehicle chosen is a simple pMOS test chip, which includes different structures such as transistors and invertors. The processing steps and sequence required to integrate TWIs into wafers with active devices is demonstrated.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116575567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power low-noise sensor IC","authors":"Haidong Guo, C.L. Champion, D. Rector, G. la Rue","doi":"10.1109/WMED.2004.1297352","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297352","url":null,"abstract":"An IC for acquisition of 16 electrophysiology signals in mice is described. Each channel includes programmable gains from 10 to 1000, a 7 kHz low-pass 4th-order Butterworth filter and a sample and hold. Simulations predict 14-bit accuracy up to 7 kHz. The integrated noise from 1 Hz to 7 kHz is 1.9 /spl mu/V/Hz/sup 1/2 /. The +/-0.3V dc input offset of each channel is cancelled with 7-bit DACs controlling the bulk of the first opamp input transistors and 6-bit DACs on the 2/sup nd/ stage. Total power dissipation is 13.5 mW using a 3V supply. Die area is 6 mm/sup 2/ in a 0.25 /spl mu/ process.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127368112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation of the exclusion/extraction InSb MOSFETs","authors":"E. Sijercic, K. Mueller, B. Pejcinovic","doi":"10.1109/WMED.2004.1297354","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297354","url":null,"abstract":"A methodology for simulation of InSb MOSFETs in standard drift-diffusion simulators is presented. Due to its low bandgap and high mobility, InSb shows promise as a material for extremely high frequency active devices operating at very low voltages. Material complexities, such as non-parabolicity, degeneracy, mobility and Auger recombination/generation are explained, and physics based models are developed. This methodology is then applied to the examination of the leakage current, transconductance and maximum unity current gain frequency of the exclusion/extraction MOSFET. Its scaling properties down to 0.15 /spl mu/m are also analyzed.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Sukumar, D. Pan, K. Buck, H. Hess, H. Li, D. Cox, M. Mojarradi
{"title":"Design of a pipelined adder using skew tolerant domino logic in a 0.35 /spl mu/m TSMC process","authors":"V. Sukumar, D. Pan, K. Buck, H. Hess, H. Li, D. Cox, M. Mojarradi","doi":"10.1109/WMED.2004.1297351","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297351","url":null,"abstract":"Over the years, there has been an increased growth in wireless electronics and distributed computer architectures. This has pushed the need for developing innovative designs for realizing fast multi-bit adders such as the carry propagate adder (CPA). To increase the frequency of operation, pipelining is considered. As the frequency of operation is increased, the cycle time measured in gate delays continues to shrink. As such, the overhead becomes more important for the design of high performance systems. This paper discusses overlapping clocks to eliminate possible sources of overhead by using the concept of time borrowing. The relationship between overlapping clock frequency and the amount of total computation time will be explored in detail. Simulation results will show output profiles for various input data patterns.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Elimination of body effects in SOI CMOS devices","authors":"S. Pemmaraju, S. Parke","doi":"10.1109/WMED.2004.1297373","DOIUrl":"https://doi.org/10.1109/WMED.2004.1297373","url":null,"abstract":"Tremendous research is going on in using silicon-on-insulator (SOI) devices for commercial purposes. Many advantages, like low junction capacitance, complete isolation of devices, smaller layout area, low power consuming circuits and lesser delays have enhanced the possibility of faster circuits. Still, problems with the parasitic floating body effects in partially depleted SOI (PDSOI) devices exist. The effects of the floating body are studied through the DC characteristics of PDSOI device structures. Effects like the kink effect, loss of gate control, self-heating effect and impact ionization are investigated. The impact ionization and the bipolar latch up effects tend to dominate in partially depleted (PDSOI) devices. DC characteristics of body tied to source, dynamic threshold MOS (DTMOS), and PDSOI devices are presented.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125099435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}