CMOS imager technology shrinks and image performance

Abstract

In this paper, we present a performance summary of CMOS imager pixels from 5.2 /spl mu/m to 4.2 /spl mu/m using 0.18 /spl mu/m imager design rules, then to 3.2 /spl mu/m using 0.15 /spl mu/m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based on technology shrinks of Micron's 2P3M imager process, and each of the technology nodes report excellent CMOS imager low-noise, high-sensitivity, low-lag, and low-light performance, matching that of state-of-the-art charged-coupled device (CCD) imagers. We have put a model in place to provide the predictive performance of smaller pixels, and then use that model to discuss performance expectations down to 2.0 /spl mu/m pixels. With the combination of imager design rules, pixel architecture, and process technology tailored for CMOS imagers, we see no fundamental reason that CMOS imagers should not be able to continue matching CCD performance as pixel sizes shrink.