Design of a pipelined adder using skew tolerant domino logic in a 0.35 /spl mu/m TSMC process

Abstract

Over the years, there has been an increased growth in wireless electronics and distributed computer architectures. This has pushed the need for developing innovative designs for realizing fast multi-bit adders such as the carry propagate adder (CPA). To increase the frequency of operation, pipelining is considered. As the frequency of operation is increased, the cycle time measured in gate delays continues to shrink. As such, the overhead becomes more important for the design of high performance systems. This paper discusses overlapping clocks to eliminate possible sources of overhead by using the concept of time borrowing. The relationship between overlapping clock frequency and the amount of total computation time will be explored in detail. Simulation results will show output profiles for various input data patterns.