Clock and data recovery circuits with fast acquisition and low jitter

Abstract

This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Fabricated in a 0.5 /spl mu/m CMOS process, the combined CDR achieves operation up to 750 Mbps. Measurements show at least a 6% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps at 688 Mbps after a PLL lock time of 700 ns. Power dissipation is 300 mW and die area is 1.4 /spl times/ 1.4 mm/sup 2/.