Metal-insulator-Si (MIS) structure for advanced DRAM cell capacitor

The conventional DRAM cell capacitor with silicon-insulator-silicon (SIS) structure limits the scaling of capacitor cell size because the depletion layer of the polycrystalline-Si electrode becomes more severe as the cell dielectrics (ONO) thickness reaches the sub-50 /spl Aring/ region. This paper demonstrates that capacitance can be significantly increased by using a metal-insulator-Si (MIS) structure where the top electrode is metal TiN and the bottom electrode is semi-hemisphere Si grain (HSG). Capacitance can be further enhanced with PH/sub 3//NH/sub 3/ anneal to the HSG. The effects of post high-temperature anneal on the stability of the MIS structure are also discussed.