{"title":"DDFS中的非线性DAC实现","authors":"Zhihe Zhou, I. Horowitz, G. la Rue","doi":"10.1109/WMED.2004.1297372","DOIUrl":null,"url":null,"abstract":"A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.","PeriodicalId":296968,"journal":{"name":"2004 IEEE Workshop on Microelectronics and Electron Devices","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Non-linear DAC implementations in DDFS\",\"authors\":\"Zhihe Zhou, I. Horowitz, G. la Rue\",\"doi\":\"10.1109/WMED.2004.1297372\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.\",\"PeriodicalId\":296968,\"journal\":{\"name\":\"2004 IEEE Workshop on Microelectronics and Electron Devices\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE Workshop on Microelectronics and Electron Devices\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WMED.2004.1297372\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE Workshop on Microelectronics and Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMED.2004.1297372","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
在直接数字频率合成器(DDFS)中减小ROM大小和功耗的一种技术是使用非线性DAC来近似正弦函数。根据所需的ROM大小、可实现的无杂散动态范围(SFDR)和实现复杂性，研究了12位、14位和16位非线性DAC的分段线性和分段二次近似。结果表明，采用16段二次逼近、14位DAC分辨率和5位平方电路可以实现94 dB SFDR。所需的ROM大小只有256位。
A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.
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