Analysis of jitter in clock distribution networks

Abstract

A technique for the simulation of jitter in clock distribution networks will be demonstrated. Noise is injected as a time domain signal into each driver stage in the clock distribution network and large signal non-linear transient simulations are performed to obtain the distribution of clock periods and the subsequent jitter in the clock signal. In the simplest case the noise is the thermal channel noise of the CMOS driver transistors, and the results can be compared to the simple analytical estimate given by Gray et al.[1994]. It will be shown that there is a good agreement between the simulation results and analytical estimates if a modified analytical formula is used where the simple estimate for delay by Gray et al. is replaced by the observed delay from simulations. The technique can be extended and is directly applicable to other types of noise such as power supply noise.