Packaging effect on reliability of Cu/low k interconnects

Abstract

In a plastic flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results to investigate the chip-package interaction and its impact on low k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low k interfaces. Then results from 3D FEA, based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry, to investigate the chip-package interaction for SiLK and MSQ low k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures.