16th Asian Test Symposium (ATS 2007)最新文献

{"title":"Special Session: Analog Production Test","authors":"F. Muradali, J. Rivoir","doi":"10.1109/ATS.2007.56","DOIUrl":"https://doi.org/10.1109/ATS.2007.56","url":null,"abstract":"In response to trends and needs in test research and development, the Asian Test Symposium introduces an ongoing crafted effort related to analog testing. Over the next few years, the goal of the Special Sessions on Analog Production Test is to examine and improve production oriented issues related to analog circuits. That is, all the steps and procedures related to the test and release of an analog part or system. Such units may be thumbnail-sized components, ultra-high precision dust sized silicon or board/chip-integrated analog systems.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126691215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resistive Bridging Faults DFT with Adaptive Power Management Awareness","authors":"Urban Ingelsson, P. Rosinger, S. S. Khursheed, B. Al-Hashimi, P. Harrod","doi":"10.1109/ATS.2007.69","DOIUrl":"https://doi.org/10.1109/ATS.2007.69","url":null,"abstract":"A key design constraint of circuits used in handheld devices is the power consumption, due mainly to the limitations of battery life. The employment of adaptive power management (APM) methods optimizes the power consumption of such circuits. This paper describes an effective APM-aware DFT technique that consists of a Test Generation Suite, including fault list generation, test pattern generation and fault simulation. The test generation suite is capable of generating test patterns for multiple supply voltage (Vdd) settings to maximize coverage of resistive bridging faults; and a method to reduce the number of Vdd settings without compromising the fault coverage in order to reduce the cost of test. Preliminarily validations of the proposed DFT technique using a number of benchmark circuits demonstrate its effectiveness.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128086667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC","authors":"L. Fang, Yang Zhong, H. V. D. Donk, Y. Xing","doi":"10.1109/ATS.2007.93","DOIUrl":"https://doi.org/10.1109/ATS.2007.93","url":null,"abstract":"In the era of Zero Defects, ICCQ is one of the powerful non-specification based testing methods to achieve high test coverage and supreme product quality. Within this project, based on the fault simulation with Defect Oriented Test (DOT) technique, the current tests with the most efficient coverage improvements have been selected and implemented in the production testing flow.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128476514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test Generation for Timing-Critical Transition Faults","authors":"X. Lin, M. Kassab, J. Rajski","doi":"10.1109/ATS.2007.120","DOIUrl":"https://doi.org/10.1109/ATS.2007.120","url":null,"abstract":"Timing-aware ATPG [1] has been shown to be an effective method for generating high-quality test sets that detect small delay defects through the longest paths. However, this method usually results in a much higher test pattern count than the traditional transition fault test generation. In this paper, we propose a new criterion that identifies a subset of transition faults to be targeted by the timing-aware ATPG in order to reduce test pattern count while minimizing the impact on the overall delay test quality. The new criterion utilizes the minimal static slack to classify certain transition faults as timing-critical. The test pattern count reduction is achieved by restricting the timing-aware ATPG to targeting the timing-critical transition faults while using traditional transition fault test generation for the remaining transition faults. The experimental results for the industrial circuits show the effectiveness of the proposed method.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Accurate Analysis of Microprocessor Design Verification","authors":"Haihua Shen, Heng Zhang","doi":"10.1109/ATS.2007.95","DOIUrl":"https://doi.org/10.1109/ATS.2007.95","url":null,"abstract":"Comparing with the passion for verification technical innovations, the practical verification experiences especially the bug reports and analyses rarely appear in public research. It is very important to analyze the practical bug reports for feedback on the future verification. Thanks to the sufficient design scale of our microprocessor and efficient verification environment we developed, we are able to present in this paper an extensive analysis of the effects of bugs on different design stages and different microarchitectures. The analysis approaches and results are valuable for estimating the distribution of bugs in a microprocessor design and preventing the project from verification bottlenecks.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing","authors":"F. Hussin, T. Yoneda, H. Fujiwara","doi":"10.1109/ATS.2007.22","DOIUrl":"https://doi.org/10.1109/ATS.2007.22","url":null,"abstract":"In this paper, a new approach to NoC test scheduling based on bandwidth-sharing is presented. The test scheduling is performed under the objective of co-optimizing the wrapper area overhead and the resulting test application time using two complementary NoC wrappers. Experimental results showed that the area overhead can be optimized (to an extent) without compromising the test application time. Compared to other NoC scheduling approaches based on dedicated paths, our bandwidth sharing approach can reduce the test application time by up to 75.4%.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Issues Regarding New Product Release in Semiconductor Manufacturing","authors":"Choon-Sang Chew","doi":"10.1109/ATS.2007.16","DOIUrl":"https://doi.org/10.1109/ATS.2007.16","url":null,"abstract":"There are varied levels of communication among the multiple development groups involved in releasing a new product. As the product creation flow is traversed, groups may make assumptions and sometimes little \"cut corners\" that are assumed to be handled by another operation. Unfortunately, the last wall over which the chip is thrown is at manufacturing. It is here where the fight, fix and payment for all those loose ends and obscure assumptions are made. With this in mind, the presentation delivers some practical issues to take into consideration when releasing new products or new equipment to semiconductor manufacturing.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimum Test Set for Bridging Fault Detection in Reversible Circuits","authors":"H. Rahaman, D. Kole, D. K. Das, B. Bhattacharya","doi":"10.1109/ATS.2007.91","DOIUrl":"https://doi.org/10.1109/ATS.2007.91","url":null,"abstract":"Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n X n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior","authors":"M. Bastian, Vincent Gouin, P. Girard, C. Landrault, A. Ney, S. Pravossoudovitch, A. Virazel","doi":"10.1109/ATS.2007.121","DOIUrl":"https://doi.org/10.1109/ATS.2007.121","url":null,"abstract":"Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127711887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test","authors":"S. Taneja","doi":"10.1109/ATS.2007.106","DOIUrl":"https://doi.org/10.1109/ATS.2007.106","url":null,"abstract":"Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production. The Test technologies need to innovate at a faster pace to enable system companies and their semiconductor suppliers - in segments ranging from automotive to entertainment and multi-media to meet these new challenges. The rapid advances in nanometer technologies pose another set of challenges, primarily related to integration. Whereas the integration at the level of interoperability amongst different tools in the design and implementation flows has been adequate in the past, nanometer technology introduces new levels of complexity due to the advanced physics effects and higher scales of transistor integration. This in turn results in complex interaction and interdependence amongst the different design steps such as synthesis, test, floor planning, placement, routing and chip finishing. The EDA industry needs to establish a new paradigm and a \"deep integration\" to meet these challenges and to deliver the productivity gains that will enable our customers to meet demands on functionality, correctness, quality and time-to-volume production. The paradigm needs to shift from \"Design For Test\" to \"Design With Test\", to fully model the tight interdependencies between design and test. During the design phase, DFT steps must integrate well during the design architecture, synthesis, timing and layout steps. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using timing and layout information. Such advances in innovation and integration will go a long way in moving the EDA industry from being a supplier of point tools to the role of a partner proactively anticipating and delivering on customers' needs. The keynote will discuss these challenges and possible solutions and scenarios.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127798163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}