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Test Compression / Decompression Based on JPEG VLC Algorithm 基于JPEG VLC算法的测试压缩/解压缩
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.60
H. Ichihara, Yukinori Setohara, Y. Nakashima, T. Inoue
{"title":"Test Compression / Decompression Based on JPEG VLC Algorithm","authors":"H. Ichihara, Yukinori Setohara, Y. Nakashima, T. Inoue","doi":"10.1109/ATS.2007.60","DOIUrl":"https://doi.org/10.1109/ATS.2007.60","url":null,"abstract":"Test data compression /decompression schemes for testing SoCs can reduce test application cost. A drawback of the previous schemes, however, is that a decompressor must be embedded in an SoC under test. In this paper, we target the testing of SoCs with multimedia cores and introduce a scheme of test compression / decompression with the decoding function in the multimedia cores. This scheme can utilize the decoder and encoder in a multimedia core for compressing and decompressing test data, and consequently it requires slight hardware overhead. As an example of the proposed scheme, we focus on a lossless variable-length coding (VLC) in the JPEG algorithm, and propose a test compression / decompression method using the VLC decoder. We also propose a test generation method for this scheme. Experimental results show that the test compression with the VLC can achieve high compression ratio and the proposed test generation method can increase the compression ratio.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114620302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements 用低成本的软容错序列元件提高电路鲁棒性
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.51
Mingjing Chen, A. Orailoglu
{"title":"Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements","authors":"Mingjing Chen, A. Orailoglu","doi":"10.1109/ATS.2007.51","DOIUrl":"https://doi.org/10.1109/ATS.2007.51","url":null,"abstract":"Soft errors induced by alpha particles and cosmic radiation have become a highly challenging problem in the design of UDSM or nanoscale circuits, making the incorporation of circuit hardening techniques essential. In this paper, a design technique for soft-error-tolerant sequential elements is presented to improve circuit robustness. The proposed technique exploits time and space redundancy using an elaborate flip-flop structure, and provides complete soft error immunity for both the transient faults generated in the combinatorial logic and the particle strikes inside the flip- flops. The proposed technique is developed to be compatible with current digital design technology, thus having minimal impact on design flow and hardware cost. Simulation results confirm the effectiveness of the proposed technique.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"580 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Concurrent Test Implementations 并发测试实现
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.101
Shawn Molavi, Toby McPheeters
{"title":"Concurrent Test Implementations","authors":"Shawn Molavi, Toby McPheeters","doi":"10.1109/ATS.2007.101","DOIUrl":"https://doi.org/10.1109/ATS.2007.101","url":null,"abstract":"Today's large SOC devices include many different IP blocks which tested sequentially add significant test time to the production flow. Testing of several devices in parallel is one way to reduce test time and cost per device. However, as more functionality is added to the SOCs, the pin count will increase and limit the number of sites that can be tested in parallel. One method to reduce test time per device is to concurrently test multiple areas of the device at the one time. Concurrent test is a methodology to test various sections of the device in parallel. This paper will discuss three different types of concurrent test. The first type of concurrent test takes advantage of the ATE's per pin electronics to perform DC or frequency measure tests in parallel. One example is running several PLL clock tests at once. A second type of concurrent test makes use of the device's DFT modes to execute simultaneous tests on different IP blocks. An example of this is executing time consuming digital tests like scan concurrently with analog tests like RF tuners or serial ATA. A third method to reduce test time is to start a new test while the previous results are still being calculated. Processing captured data can be done at the same time other tests are being executed. This could be applied to the outputs of ADCs or DACs where large amounts of data are processed by one or more embedded processors in the ATE while subsequent tests are running. Some of these techniques require the implementation of DFT at design time to allow multiple blocks to function simultaneously and independently of each other. The test board must also be designed with careful consideration to concurrent test. The ATE will play a key role in that it must support concurrent test features in its hardware and software. Implementing concurrent test will result in higher throughput and lower test cost which every semiconductor company must obtain to stay competitive.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124982680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects 高mdsi:用于互连的高水平信号完整性故障测试模式生成方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.58
S. Chun, YongJoon Kim, Sungho Kang
{"title":"High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects","authors":"S. Chun, YongJoon Kim, Sungho Kang","doi":"10.1109/ATS.2007.58","DOIUrl":"https://doi.org/10.1109/ATS.2007.58","url":null,"abstract":"Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE- based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115933233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs CAMEL:一种高效的CAMs耦合故障仿真器
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.27
Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
{"title":"CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs","authors":"Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu","doi":"10.1109/ATS.2007.27","DOIUrl":"https://doi.org/10.1109/ATS.2007.27","url":null,"abstract":"Content addressable memories (CAMs) are widely used in digital systems. A test algorithm for CAMs must be able to cover the random access memory (RAM) faults and comparison faults. However, CAM circuits are usually customized for different products, so there are no standard tests, i.e., tests should be adapted to a specific design manufactured using specific technology. This paper presents a fault simulator, called CAM Evaluation tooL (CAMEL), for the evaluation of fault coverage of CAM test algorithms. It supports five common functional outputs, i.e., Data I/O, hit, multi-hit, matchout, and priority address for various CAM specifications. Since coupling fault simulation dominates the efficiency of a memory fault simulator, a concept of observability is proposed to simplify the coupling fault behavior. By exploiting the observability, a compression technique is also proposed to speed up the fault simulation and reduce memory usage. CAMEL can support both RAM faults and comparison faults. We have demonstrated the CAMEL using widely-used March tests and CAM tests. Simulation results show that the CAMEL can evaluate the fault coverage of tests accurately and efficiently.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"624 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE 动态重新配置多端口ATE的soc多频模块化测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.79
Dan Zhao, Ronghua Huang, H. Fujiwara
{"title":"Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE","authors":"Dan Zhao, Ronghua Huang, H. Fujiwara","doi":"10.1109/ATS.2007.79","DOIUrl":"https://doi.org/10.1109/ATS.2007.79","url":null,"abstract":"With the debut of a new class of multi-port ATE (e.g., Agilent 93000 series), there is a pressing need for test planning methods to fully adapting SoC test framework design to the new concurrent test capabilities and fulfil emerging demands of high-speed testing. In this paper, we propose a new test planning strategy that addresses multi-frequency SoC testing by dynamically reconfiguring ATE ports. The system integrators on-the-fly group pins into virtual ports while ATE ports simultaneously drive the testing of a set of cores at multiple independent clock domains. An effective and efficient system optimization technique is developed to manage test resources and improve test efficiency for modern complex SoC designs.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116941461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A BIST Technique for RF Voltage-Controlled Oscillators 射频压控振荡器的BIST技术
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.31
H. Hsieh, Yen-Chih Huang, Liang-Hung Lu, G. Huang
{"title":"A BIST Technique for RF Voltage-Controlled Oscillators","authors":"H. Hsieh, Yen-Chih Huang, Liang-Hung Lu, G. Huang","doi":"10.1109/ATS.2007.31","DOIUrl":"https://doi.org/10.1109/ATS.2007.31","url":null,"abstract":"A built-in self-test (BIST) architecture is proposed for voltage-controlled oscillators (VCO) operating at multi- gigahertz frequencies. By utilizing a frequency divider and a frequency-to-voltage converter (FVC), the output frequency and tuning range of the VCO can be extracted without external test instruments. The proposed BIST module is integrated with a wideband VCO as the DUT in a 0.18-mum CMOS process for demonstration. Within the tuning range of the VCO from 4.4 to 5.5 GHz, a frequency extraction error less than plusmn0.4% is achieved. The active area and the power consumption of the BIST module are 0.038 mm2 and 11 mW, respectively.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129421342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability 基于布尔可满足性的诊断测试模式生成框架
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-01 DOI: 10.1109/ATS.2007.80
Feijun Zheng, K. Cheng, Xiaolang Yan, J. Moondanos, Z. Hanna
{"title":"An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability","authors":"Feijun Zheng, K. Cheng, Xiaolang Yan, J. Moondanos, Z. Hanna","doi":"10.1109/ATS.2007.80","DOIUrl":"https://doi.org/10.1109/ATS.2007.80","url":null,"abstract":"This paper presents a diagnostic test pattern generation (DTPG) framework based upon a Boolean Satisfiability engine. We first propose an enhanced miter-based model for distinguishing fault candidates that can achieve greater efficiency as well as can prove a group of undifferentiable faults. The model can also be used to generate diagnostic tests for distinguishing faults of different fault types. Based on this model, we propose a diagnostic pattern compaction strategy. By exploring \"don't cares \" at the primary inputs, the number of required diagnostic patterns can be reduced. Experimental results show that the proposed method achieves a greater diagnosis resolution when combined with existing approaches. Also, fewer diagnostic test patterns are needed.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130132504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories 多异构嵌入式存储器的混合BIST方案
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-01 DOI: 10.1109/ATS.2007.12
Li-Ming Denq, Cheng-Wen Wu
{"title":"A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories","authors":"Li-Ming Denq, Cheng-Wen Wu","doi":"10.1109/ATS.2007.12","DOIUrl":"https://doi.org/10.1109/ATS.2007.12","url":null,"abstract":"It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to high routing penalty from the BIST circuits. Previous BIST schemes solve the problem using serial interface, e.g., based on the IEEE 1500 architecture and novel scan approaches, to reduce the routing area overhead. However, serial approaches do not allow at-speed test and diagnosis, and are very slow. In this paper, we propose a hybrid BIST architecture that reduces the routing penalty, while allowing at-speed test and diagnosis of the memory cores. The test time is close to that of a typical parallel BIST method. Experimental results show that the proposed BIST can effectively reduce the area overhead.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115908416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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