Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE

Abstract

With the debut of a new class of multi-port ATE (e.g., Agilent 93000 series), there is a pressing need for test planning methods to fully adapting SoC test framework design to the new concurrent test capabilities and fulfil emerging demands of high-speed testing. In this paper, we propose a new test planning strategy that addresses multi-frequency SoC testing by dynamically reconfiguring ATE ports. The system integrators on-the-fly group pins into virtual ports while ATE ports simultaneously drive the testing of a set of cores at multiple independent clock domains. An effective and efficient system optimization technique is developed to manage test resources and improve test efficiency for modern complex SoC designs.