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Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique 响应反转扫描单元(RISC):一种峰值捕获功率降低技术
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.74
Bo Chen, W. Kao, B. Bai, Shyue-Tsong Shen, J. Li
{"title":"Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique","authors":"Bo Chen, W. Kao, B. Bai, Shyue-Tsong Shen, J. Li","doi":"10.1109/ATS.2007.74","DOIUrl":"https://doi.org/10.1109/ATS.2007.74","url":null,"abstract":"This paper presents a response inversion scan cell (RISC) technique to reduce the peak capture power in test mode. The RISC technique inverts the data input of selected scan cells so that peak capture power is reduced. According to the experimental data on ISCAS'89 benchmark circuits, the RISC technique effectively reduces the peak capture power by 45% at a cost of 7.6% area overhead. The presented technique requires minimum change in the existing design for testability (DFT) methodology and it does not degrade fault coverage. The RISC technique is validated by a chip experiment on a 0.18 mum low power design.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement 一种用于抖动测量的2ps分辨率宽范围BIST电路
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.46
N. Cheng, Yu Lee, Ji-Jan Chen
{"title":"A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement","authors":"N. Cheng, Yu Lee, Ji-Jan Chen","doi":"10.1109/ATS.2007.46","DOIUrl":"https://doi.org/10.1109/ATS.2007.46","url":null,"abstract":"In this paper, we propose a novel built-in self-test (BIST) circuit to directly measure cycle-to-cycle jitter. The clock-under-test is under-sampled by this measurement circuit and the jitter values are transformed into digital words. A time-amplified technique is applied to obtain relatively higher resolution with smaller hardware overhead. Experimental results show that our proposed circuit is able to measure the jitter providing the clock frequency up to 2 GHz with resolution of 2 picoseconds.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Built-In Speed Grading with a Process-Tolerant ADPLL 内置速度分级与进程容忍ADPLL
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.38
H. Hsu, Chun-Chieh Tu, Shi-Yu Huang
{"title":"Built-In Speed Grading with a Process-Tolerant ADPLL","authors":"H. Hsu, Chun-Chieh Tu, Shi-Yu Huang","doi":"10.1109/ATS.2007.38","DOIUrl":"https://doi.org/10.1109/ATS.2007.38","url":null,"abstract":"Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry. This Built-in Speed Grading (BISG) methodology uses an All-Digital Phase-Locked Loop (ADPLL) as the programmable clock generator to provide various clock signals within a specific frequency range. The maximum operating speed of a circuit can thus be easily tracked down using a binary search process with multiple runs of built-in self-test. To accommodate larger process variation, we further explore a so-called binary-neighborhood-linear frequency-locking scheme for the underlying ADPLL, and thereby resulting in a higher accuracy. Experimental results show that only 2289 gates are adequate to provide this valuable infrastructure that may find numerous applications in IC testing and diagnostics.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123037061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The Region-Exhaustive Fault Model 区域穷举故障模型
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.78
A. Jas, S. Natarajan, S. Patil
{"title":"The Region-Exhaustive Fault Model","authors":"A. Jas, S. Natarajan, S. Patil","doi":"10.1109/ATS.2007.78","DOIUrl":"https://doi.org/10.1109/ATS.2007.78","url":null,"abstract":"Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Reconsideration of Software Reliability Measurements 软件可靠性测量的重新考虑
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.39
Shiyi Xu
{"title":"Reconsideration of Software Reliability Measurements","authors":"Shiyi Xu","doi":"10.1109/ATS.2007.39","DOIUrl":"https://doi.org/10.1109/ATS.2007.39","url":null,"abstract":"In this paper, we discuss the major weaknesses of the software reliability measurements currently used and propose a new model of software reliability estimation. For the time being, the software reliability models are employed far from ubiquitous. As a national research project, we propose some strategies of improving the software reliability measurement. The central idea of the strategies proposed in this paper is to incorporate the influence factors of complexity of the software under test and the test effectiveness into the software reliability models so as to make the software reliability models more adequate and accurate to the real situation. Results from substantial experiments have shown the rationality and usefulness of the new model.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116478679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides EDA, ATE, IP和Fab的下一代测试，诊断和良率挑战-从各个方面来看
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.111
Yasuharu Kohiyama, C. Ravikumar, Yasuo Sato, Laung-Terng Wang, Y. Zorian
{"title":"Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides","authors":"Yasuharu Kohiyama, C. Ravikumar, Yasuo Sato, Laung-Terng Wang, Y. Zorian","doi":"10.1109/ATS.2007.111","DOIUrl":"https://doi.org/10.1109/ATS.2007.111","url":null,"abstract":"The Test industry has come a long way over the past few decades. As a whole we have made great strides in the areas of:","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127767944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Efficiency Analysis and Improvement of SOC Test Platforms SOC测试平台的测试效率分析与改进
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.67
Tong-Yu Hsieh, Kuen-Jong Lee, Jianyu You
{"title":"Test Efficiency Analysis and Improvement of SOC Test Platforms","authors":"Tong-Yu Hsieh, Kuen-Jong Lee, Jianyu You","doi":"10.1109/ATS.2007.67","DOIUrl":"https://doi.org/10.1109/ATS.2007.67","url":null,"abstract":"Employing a test platform in an SOC design has been shown to be an effective method for SOC testing. However the test efficiency problem of a test platform has not been addressed. In this paper, we formally analyze the test efficiency of test platforms and seek for its optimization. We formulate the required numbers of test cycles for test platforms implemented with different test structures and/or executed with different test procedures. It is shown that up to 24X test time difference for platforms with different test structures/procedures is possible. Based on the derived formula, an appropriate test platform that can achieve best test efficiency with minimal area overhead can be determined.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults 基于延迟故障现实假设改进串扰时序无关测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.86
Shahdad Irajpour, S. Gupta, M. Breuer
{"title":"Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults","authors":"Shahdad Irajpour, S. Gupta, M. Breuer","doi":"10.1109/ATS.2007.86","DOIUrl":"https://doi.org/10.1109/ATS.2007.86","url":null,"abstract":"Test generation methodology previously developed for crosstalk targets in the presence of manufacturing defects and process variations results in low coverage. In this paper, under a realistic assumption about the nature of manufacturing defects, we show that by incorporating two new concepts, namely, non- criticality and delay-superiority, significantly higher coverage of targets and lower test generation and test application costs are achieved.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134390243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan 触发器选择最大化TDF覆盖与部分增强扫描
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.96
Gefu Xu, A. Singh
{"title":"Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan","authors":"Gefu Xu, A. Singh","doi":"10.1109/ATS.2007.96","DOIUrl":"https://doi.org/10.1109/ATS.2007.96","url":null,"abstract":"Enhanced scan designs support high coverage TDF testing but with significant overhead. We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the TDF coverage benefits of enhanced scan can be achieved at 10-30% of the cost.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132605597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Enhanced Broadside Testing for Improved Transition Fault Coverage 增强舷侧测试，提高过渡故障覆盖率
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.85
I. Pomeranz, S. Reddy
{"title":"Enhanced Broadside Testing for Improved Transition Fault Coverage","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2007.85","DOIUrl":"https://doi.org/10.1109/ATS.2007.85","url":null,"abstract":"The use of multiple scan chains was shown to improve the coverage of transition faults achieved by skewed-load tests. For broadside tests, the number of scan chains does not affect the transition fault coverage. We describe an enhanced broadside configuration under which increasing the number of scan chains helps increase the fault coverage. In the enhanced configuration, the first flip-flop of a scan chain operates in skewed-load mode while the other flip-flops operate in broadside mode. This provides flexibility in determining the value of the first flip-flop of every scan chain under the second pattern of a broadside test, thus increasing the transition fault coverage. We also describe a procedure that makes small modifications to a given scan chain configuration in order to improve the transition fault coverage.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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