16th Asian Test Symposium (ATS 2007)最新文献_第9页

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects 考虑多重耦合效应的串扰故障测试生成

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.30

M. Zhang, Xiaowei Li

引用次数: 4

Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering 通过修改扫描结构和重新排序测试向量来降低扫描功耗

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.23

C. Giri, Pradeep Kumar Choudhary, S. Chattopadhyay

引用次数: 3

System Testing using UML Models 使用UML模型进行系统测试

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.102

M. Sarma, R. Mall

引用次数: 10

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs 通过指定最小控制输入集来产生低捕获功率测试

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.32

Nan-Cheng Lai, Sying-Jyan Wang

引用次数: 5

An HDL-Based Platform for High Level NoC Switch Testing 基于hdl的高电平NoC开关测试平台

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.97

Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Z. Navabi

引用次数: 13

CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors CREA:一个基于检查点的可靠的超标量处理器微体系结构

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.19

Shijian Zhang, Weiwu Hu

引用次数: 0

Experimental Results of Transition Fault Simulation with DC Scan Tests 用直流扫描试验模拟过渡故障的实验结果

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.50

Wataru Kawamura, Takeshi Onodera

引用次数: 1

Invited Talk 1: Testing of Power Constraint Computing 特邀演讲1:功率约束计算的测试

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.107

T. M. Mak

{"title":"Invited Talk 1: Testing of Power Constraint Computing","authors":"T. M. Mak","doi":"10.1109/ATS.2007.107","DOIUrl":"https://doi.org/10.1109/ATS.2007.107","url":null,"abstract":"Summary form only given. Computing trend has taken a right hand turn. Instead of utmost performance at any cost, performance level have to be capped with the maximum power dissipation affordable at any given platform. With thermal dissipation mechanisms and energy cost as the primary drivers, computing at any level, from handheld devices to high-end servers, have to be power constraint. Various innovations arise to this challenge: Clock gating, power gating (sleep) transistors, multiple (and individually controlled) power supplies and power regions, fine grain frequency and power control, in-package Voltage Regulator Module, just to name a few. The power issues are also driving some interesting architectural and interconnect/packaging options into the main stream. While there have been innovations in the Test area for the past 25 years, including advanced fault models, such as bridges and opens, various favors of transition, delay path, crosstalk and the various ATPG that support them, power related test innovations have been seriously lacking. Power related testing issues have mostly been restricted to those of scan shifting and matching up of average power consumption. More recently, some papers have pointed to fast (launch and capture) clock related power transients and IR drops related issues, but the solutions is still far from being able to mimic the real situations and solve real world test problems. This talk will mostly focus on the test implications of power constraints over the spectrum of computing products. These implications are also intertwined with extreme process scaling to make conventional testing paradigm no longer valid. Some discussions of the various test options to deal with the power issues will also be reviewed.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Test Roles in Diagnosis and Silicon Debug 诊断和硅调试中的测试角色

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.112

A. Uzzaman, F. Muradali, T. Aikyo, R. Aitken, Tom Jackson, R. Galivanche, Takeshi Onodera

{"title":"Test Roles in Diagnosis and Silicon Debug","authors":"A. Uzzaman, F. Muradali, T. Aikyo, R. Aitken, Tom Jackson, R. Galivanche, Takeshi Onodera","doi":"10.1109/ATS.2007.112","DOIUrl":"https://doi.org/10.1109/ATS.2007.112","url":null,"abstract":"Test catches defective parts. Traditional DFT makes test-related activities more cost effective. Debug and diagnosis discovers why a design or part did not work. Yield relates to how many good parts can be shipped thus how many dollars can be received. As one would expect, all these areas are related. The issue becomes: Can information from one operation be geared to better another? This panel specifically considers how test/ DFT can aid in debug & diagnosis. The discussion is then extended to capture the impact on yield management in riskier contemporary and future processes. Over the past few decades, each of the above domains have gone through cycles of research, development, maturity and overhaul to adapt to changes in the process & product environment. In fact, because increasing degrees of uncertainty is introduced with modern nanometer processes, debug & diagnosis and yield management are becoming more recognized and valued portions of the product creation flow. To forward this, test and DFT functions are experiencing re-development. In building, executing and sustaining a competence, key issues include time & information. That is, the problem must be understood, solved in for the short term and solved for the long term. In addition, solution scope must be properly framed and, if possible, adaptable to unexpected changes in the process and tooling environments. It is well recognized that information availability and access are pillars of a debug/ diagnosis solution. DFT structures, design automation tooling, test programs, ATE applications and physical failure analysis are means to a bulk of this data. The follow through is the assimilation of this data into a yield management and test quality system. As the topic is broad, panel of test experts will focus on practical experiences concerning the use of test, crafted DFT or test environments to facilitate debug and diagnosis. Precise developments in tying debug/ diagnosis to yield management will also be discussed.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131120551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Testing RF Components with Supply Current Signatures 测试具有电源电流特征的射频元件

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.87

S. S. Akbay, Shreyas Sen, A. Chatterjee

引用次数: 6