Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs

Abstract

We propose a low capture power test generation method to address the capture power issue in scan-based designs. The proposed approach tries to find a minimum set of input values to determine the output values and thus leave as many X-bits in the input side as possible. These X-bits can be assigned to values that minimize capture power. In the proposed method, the global information of circuit structure is considered to reduce the appearance of unnecessary inconsistent assignments in X-filling procedure. As a result, the algorithm runs similar to previous methods in worst case. Experimental results show that the proposed method provides a better result than previous method and the approach can be adopted with any other advanced test pattern generator.