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16th Asian Test Symposium (ATS 2007)最新文献

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Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology 特邀演讲3:先进技术的铸造全尺寸可靠性测试能力设置
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.109
Kary Chien
{"title":"Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology","authors":"Kary Chien","doi":"10.1109/ATS.2007.109","DOIUrl":"https://doi.org/10.1109/ATS.2007.109","url":null,"abstract":"Summary form only given. To facilitate the business fast-growing and meet reliability test requirements of advanced technology development and multiple types of products, it is necessary to establish a flexible, fast-responsible, and efficient full-scale reliability testing capability. The reliability testing capability should cover all segments including technology development and qualification, process monitor and reliability assessment of process issues. Innovative test structure like matrix gate oxide structure was designed to improve wafer level reliability (WLR) test efficiency and probe contact resistance (PCR) calibration tool was developed to enhance test accuracy. The side braze assembly (SBA) line was established and significantly reduced the sample preparation cycle time. Moreover, it provides the flexibility to support complicated ESD/ function & design verifications, and product reliability studies using our innovative high-pin-count package solutions. Anti-ESD solution kits were developed to prevent ESD damage during sample preparation & package reliability testing in advanced technology node. Advanced test during burn in (TDBI) system was established to extend the test capability from memory device to mix-signal device. In-house Chip probing (CP) system deepens our understanding on correlation among CP, final test (FT) and reliability performance. Build-in reliability diagnosis system (BIRDS) was formed to manage the reliability data and ensures data integrity. It also creates an opportunity for reliability data systematical statistic analysis.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"76 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131013491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding 一种提高LFSR播种压缩率的高压缩短测试序列测试压缩技术
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.52
Seongmoon Wang, Wenlong Wei, S. Chakradhar
{"title":"A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding","authors":"Seongmoon Wang, Wenlong Wei, S. Chakradhar","doi":"10.1109/ATS.2007.52","DOIUrl":"https://doi.org/10.1109/ATS.2007.52","url":null,"abstract":"This paper presents a test data compression scheme that can be used to further improve compressions achieved by LFSR reseeding. The proposed compression technique can be implemented with very low hardware overhead. Unlike most commercial test data compression tools, the proposed method requires no special ATPG that is customized for the proposed scheme and can be used to compress test patterns generated by any ATPG tool. The test data to be stored in the ATE memory are much smaller than that for previously published schemes and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the number of patterns comparable to that of highly compacted deterministic patterns.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123826714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Block Marking and Updating Coding in Test Data Compression for SoC SoC测试数据压缩中的块标记与更新编码
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.57
Lei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang
{"title":"Block Marking and Updating Coding in Test Data Compression for SoC","authors":"Lei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang","doi":"10.1109/ATS.2007.57","DOIUrl":"https://doi.org/10.1109/ATS.2007.57","url":null,"abstract":"A novel test data compression coding scheme, block marking and updating coding, is proposed in this paper. Test data in the test set was divided into successive fixed-length vectors, called blocks, and then they were marked according to their compatibility compared with a reference vector. An operation that is similar to difference and a technique that strategically fills in don 't-care bits are combined to increase the probabilities of compatibility or inverse compatibility. It effectively compresses test data and its decompression structure is very simple. Experimental results of ISCAS-89 benchmark circuits show that the scheme is very effective.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130287411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault-dependent/independent Test Generation Methods for State Observable FSMs 状态可观察fsm的故障依赖/独立测试生成方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.59
Toshinori Hosokawa, Ryoichi Inoue, H. Fujiwara
{"title":"Fault-dependent/independent Test Generation Methods for State Observable FSMs","authors":"Toshinori Hosokawa, Ryoichi Inoue, H. Fujiwara","doi":"10.1109/ATS.2007.59","DOIUrl":"https://doi.org/10.1109/ATS.2007.59","url":null,"abstract":"Since scan testing is not based on the function of the circuit, but rather its structure, this method is considered to be a form of over testing or under testing. It is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical testing and timing testing. This paper proposes two test generation methods, a fault-independent test generation method and a fault-dependent test generation method, for state-observable FSMs. We give experimental results for MCNC'91 benchmark circuits. The quality and cost of the logic testing and timing testing for proposed test generation methods was evaluated.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122621902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults 基于RTL信息的假路径识别及其在延迟故障过测试减少中的应用
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.70
Yuki Yoshikawa, S. Ohtake, H. Fujiwara
{"title":"False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults","authors":"Yuki Yoshikawa, S. Ohtake, H. Fujiwara","doi":"10.1109/ATS.2007.70","DOIUrl":"https://doi.org/10.1109/ATS.2007.70","url":null,"abstract":"While design-for-testability (DFT) techniques are generally used in order to reduce test generation complexity, they induce over-testing problems. In general, DFT techniques make a large number of untestable paths testable. However delay on the path that becomes testable does not affect circuit performance because the path was originally untestable. Therefore we consider testing such path to be over-testing. In this work, we reduce the over-testing by identifying false paths using register transfer level information. Our method identifies a subset of false paths within a reasonable time. Experimental results for some RTL benchmark circuits show the effectiveness of our false path identification method.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123962609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources 基于傅立叶谱的特征测试:使用低性能测试资源进行可靠射频测试的遗传CAD工具箱
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.98
G. Srinivasan, A. Chatterjee, Vishwanath Natarajan
{"title":"Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources","authors":"G. Srinivasan, A. Chatterjee, Vishwanath Natarajan","doi":"10.1109/ATS.2007.98","DOIUrl":"https://doi.org/10.1109/ATS.2007.98","url":null,"abstract":"At the present time, coordinated EDA tools for RF/mixed-signal pin test do not exist. In this paper, a CAD tool for efficient production testing of high- performance RF systems using low-cost baseband ATE is presented The CAD tool consists of a custom developed genetic ATPG for spectral (Fourier spectrum) signature-based alternate (to full specification-based tests) test of RF systems and involves co-simulation of scalable behavioral-level models of the RF System-Under-Test, baseband ATE test instrumentation, loadboard resources, and DfT resources for fast test vector optimization/generation. The CAD tool also enables the evaluation of various low-cost ATE architectures on the impact of the generated tests to provide a cost-effective solution.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124265581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fast Bridging Fault Diagnosis using Logic Information 基于逻辑信息的快速桥接故障诊断
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.75
A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
{"title":"Fast Bridging Fault Diagnosis using Logic Information","authors":"A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/ATS.2007.75","DOIUrl":"https://doi.org/10.1109/ATS.2007.75","url":null,"abstract":"In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models. It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error. Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124319808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy 纳米技术中的IDDQ测试挑战:制造测试策略
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.36
Yu Wei P'ng, Moo Kit Lee, P. W. Ng, Chin Hu Ong
{"title":"IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy","authors":"Yu Wei P'ng, Moo Kit Lee, P. W. Ng, Chin Hu Ong","doi":"10.1109/ATS.2007.36","DOIUrl":"https://doi.org/10.1109/ATS.2007.36","url":null,"abstract":"The implementation of IDDQ test is increasingly challenging with the shrinking of process geometry in nanotechnologies. This paper presents a case study of the test challenges that the industry is facing in deep submicron process. An IDDQ manufacturing test strategy is discussed to address the challenges.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells 具有非对称单元的三元内容可寻址存储器的比较故障测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.68
Jin-Fu Li
{"title":"Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells","authors":"Jin-Fu Li","doi":"10.1109/ATS.2007.68","DOIUrl":"https://doi.org/10.1109/ATS.2007.68","url":null,"abstract":"Ternary content addressable memory (TCAM) is one key component in the dedicated hardware modulars for high-performance networking applications. Symmetric and asymmetric cells are two widely used cell structures in TCAMs. An asymmetric cell consists of a binary content addressable memory (BCAM) bit and a mask bit. This paper proposes two march-like test algorithms, TH it an TPAE, to cover the comparison faults of the BCAM cell and the comparison logic faults of the masking cell. Tan requires IN Write operations and (3N+2B) Compare operations to cover the comparison faults of an NtimesB-bit TCAM with Hit output only. TPAE requires 4N Write operations and (3N+2B) Compare operations to cover the comparison faults of an NtimesB-bit TCAM with priority address encoder (PAE) output.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125716925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation of a BIST Technique for CMOS Imagers CMOS成像仪的BIST技术评价
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.62
L. Lizarraga, S. Mir, G. Sicard
{"title":"Evaluation of a BIST Technique for CMOS Imagers","authors":"L. Lizarraga, S. Mir, G. Sicard","doi":"10.1109/ATS.2007.62","DOIUrl":"https://doi.org/10.1109/ATS.2007.62","url":null,"abstract":"This paper evaluates a new Built-In-Self-Test (BIST) technique for CMOS imagers. The test stimuli are based on applying electrical pulses at the pixel photodiode anode in order to carry out a purely electrical test. The aim of this work is to eliminate some, if not all, optical tests of the pixel matrix to reduce time and cost during production testing at a wafer level. The quality of the BIST technique is evaluated by computing test metrics such as fault coverage for catastrophic and single parametric faults, and pixel fault acceptance and fault rejection under process deviations for two different pixel architectures.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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