Invited Talk 1: Testing of Power Constraint Computing

Abstract

Summary form only given. Computing trend has taken a right hand turn. Instead of utmost performance at any cost, performance level have to be capped with the maximum power dissipation affordable at any given platform. With thermal dissipation mechanisms and energy cost as the primary drivers, computing at any level, from handheld devices to high-end servers, have to be power constraint. Various innovations arise to this challenge: Clock gating, power gating (sleep) transistors, multiple (and individually controlled) power supplies and power regions, fine grain frequency and power control, in-package Voltage Regulator Module, just to name a few. The power issues are also driving some interesting architectural and interconnect/packaging options into the main stream. While there have been innovations in the Test area for the past 25 years, including advanced fault models, such as bridges and opens, various favors of transition, delay path, crosstalk and the various ATPG that support them, power related test innovations have been seriously lacking. Power related testing issues have mostly been restricted to those of scan shifting and matching up of average power consumption. More recently, some papers have pointed to fast (launch and capture) clock related power transients and IR drops related issues, but the solutions is still far from being able to mimic the real situations and solve real world test problems. This talk will mostly focus on the test implications of power constraints over the spectrum of computing products. These implications are also intertwined with extreme process scaling to make conventional testing paradigm no longer valid. Some discussions of the various test options to deal with the power issues will also be reviewed.