主题演讲2:电子和纳米技术的消费化:对测试的影响

S. Taneja
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引用次数: 0

摘要

测试一直被认为是设计和制造之间的桥梁。然而,设计和测试工具的创新和深度集成并没有跟上电子产品消费化和快速发展的纳米集成电路设计和制造的步伐。因此,Test的全部潜力还没有被主流半导体社区所利用。电子产品的消费化对低功耗、正确性和批量生产时间提出了新的重大要求。测试技术需要以更快的速度进行创新,以使系统公司及其半导体供应商——从汽车到娱乐和多媒体领域——能够应对这些新的挑战。纳米技术的快速发展带来了另一组挑战,主要与集成有关。过去,在设计和实现流程中,不同工具之间的互操作性水平上的集成已经足够,而纳米技术由于先进的物理效应和更高规模的晶体管集成而引入了新的复杂性水平。这反过来又导致了不同设计步骤之间复杂的相互作用和相互依赖,例如合成,测试,地板规划,放置,路由和芯片整理。EDA行业需要建立一个新的范例和“深度集成”来应对这些挑战,并提供生产力收益,使我们的客户能够满足对功能、正确性、质量和批量生产时间的要求。范例需要从“为测试而设计”转变为“与测试一起设计”,以完全模拟设计和测试之间紧密的相互依赖关系。在设计阶段,DFT步骤必须在设计架构、综合、时序和布局步骤中很好地集成。随后,在制造阶段,必须无缝地利用DFT的优势进行基于良率学习的快速扫描诊断,不仅使用来自设计数据库的逻辑信息,还使用时序和布局信息。这种创新和集成方面的进步将在很大程度上推动EDA行业从点工具的供应商转变为主动预测和交付客户需求的合作伙伴的角色。主题演讲将讨论这些挑战以及可能的解决方案和场景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test
Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production. The Test technologies need to innovate at a faster pace to enable system companies and their semiconductor suppliers - in segments ranging from automotive to entertainment and multi-media to meet these new challenges. The rapid advances in nanometer technologies pose another set of challenges, primarily related to integration. Whereas the integration at the level of interoperability amongst different tools in the design and implementation flows has been adequate in the past, nanometer technology introduces new levels of complexity due to the advanced physics effects and higher scales of transistor integration. This in turn results in complex interaction and interdependence amongst the different design steps such as synthesis, test, floor planning, placement, routing and chip finishing. The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges and to deliver the productivity gains that will enable our customers to meet demands on functionality, correctness, quality and time-to-volume production. The paradigm needs to shift from "Design For Test" to "Design With Test", to fully model the tight interdependencies between design and test. During the design phase, DFT steps must integrate well during the design architecture, synthesis, timing and layout steps. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using timing and layout information. Such advances in innovation and integration will go a long way in moving the EDA industry from being a supplier of point tools to the role of a partner proactively anticipating and delivering on customers' needs. The keynote will discuss these challenges and possible solutions and scenarios.
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