16th Asian Test Symposium (ATS 2007)最新文献

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Low Power Reduced Pin Count Test Methodology 低功耗减少引脚数测试方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.81
K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li, V. Chickermane
{"title":"Low Power Reduced Pin Count Test Methodology","authors":"K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li, V. Chickermane","doi":"10.1109/ATS.2007.81","DOIUrl":"https://doi.org/10.1109/ATS.2007.81","url":null,"abstract":"This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault Dictionary Based Scan Chain Failure Diagnosis 基于故障字典的扫描链故障诊断
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.43
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
{"title":"Fault Dictionary Based Scan Chain Failure Diagnosis","authors":"Ruifeng Guo, Yu Huang, Wu-Tung Cheng","doi":"10.1109/ATS.2007.43","DOIUrl":"https://doi.org/10.1109/ATS.2007.43","url":null,"abstract":"In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122698873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2) 基于GF(2)残差多项式系统的快速低成本HW位映射内存测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.48
J. Rivoir
{"title":"Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2)","authors":"J. Rivoir","doi":"10.1109/ATS.2007.48","DOIUrl":"https://doi.org/10.1109/ATS.2007.48","url":null,"abstract":"At-speed memory test demands increasing address rates from ATE bit maps. Today, the effective address rate is multiplied using multiple costly time-interleaved bit map copies. For the first time, address permutation is investigated for memory test in an attempt to multiply the address rate without increasing the overall memory size. However all published schemes create conflicts for some addresses sequences or require too many memories. This paper introduces a novel address partitioning scheme for arbitrarily few memories M = 2mu at the expense of an increased buffer per memory. For relevant address sequences which are based on powers of two, analytical considerations and exhaustive simulations prove that the effective address rate is increased by a factor of M , with zero memory size overhead.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115661545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead 以最小的内存开销提高因果诊断的性能
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.47
Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou
{"title":"Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead","authors":"Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou","doi":"10.1109/ATS.2007.47","DOIUrl":"https://doi.org/10.1109/ATS.2007.47","url":null,"abstract":"Effect-cause diagnosis procedures are the most commonly used in industry to diagnose VLSI circuits that fail manufacturing test or field applications. Fast and effective diagnosis procedures are essential to diagnose large numbers of failing dies for yield ramp-up. We have recently proposed a method to speed up effect-cause diagnosis procedures by using a dictionary of small size [26]. In this paper we propose methods to further reduce the dictionary size and still achieve higher performance. Experiments on several industrial designs demonstrate that, on average, effect-cause diagnosis procedures can be speeded up by 3.5X while requiring minimal memory overhead for a very small dictionary.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122921689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Optimized Assignment Coverage Computation in Formal Verification of Digital Systems 数字系统形式化验证中的优化分配覆盖计算
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.40
Majid Nabi, H. Shojaei, S. Mohammadi, Z. Navabi
{"title":"Optimized Assignment Coverage Computation in Formal Verification of Digital Systems","authors":"Majid Nabi, H. Shojaei, S. Mohammadi, Z. Navabi","doi":"10.1109/ATS.2007.40","DOIUrl":"https://doi.org/10.1109/ATS.2007.40","url":null,"abstract":"Model checking thoroughly verifies the design correctness with respect to a specification. When the verification process succeeds, we can only postulate the correctness of the design relative to the given specification. How far can we affirm the verified design implements all the behavior of the desired system? With this regard we need to estimate the completeness of the properties by using some coverage metrics. In this paper, we have proposed a new metric called assignment coverage and an optimized method to overcome the intensive computations required for the multiple transformations among the abstract layers in the verification tool. The proposed coverage computation method provides adequate information to complete the set of properties. Finally, we have applied the proposed metric to some verification benchmark to reveal the effectiveness of this metric in finding undetected coverage holes.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121920838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost 扫描测试,完全覆盖路径延迟故障,减少测试数据量,测试应用时间和硬件成本
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.20
D. Xiang, K. Chakrabarty, D. Hu, H. Fujiwara
{"title":"Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost","authors":"D. Xiang, K. Chakrabarty, D. Hu, H. Fujiwara","doi":"10.1109/ATS.2007.20","DOIUrl":"https://doi.org/10.1109/ATS.2007.20","url":null,"abstract":"A new scan architecture, called enhanced scan forest, is proposed to detect path delay faults and reduce test stimulus data volume, test response data volume, and test application time. The enhanced scan forest architecture groups scan flip- flops together, where all scan flip-flops in the same group are assigned the same value for all test vectors. All scan flip- flops in the same group share the same hold latch, and the enhanced scan forest architecture makes the circuit work in the same way as a conventional enhanced scan design. The area overhead of the proposed enhanced scan forest is greatly reduced compared to that for enhanced scan design. A low- area-overhead zero-aliasing test response compactor is designed for path delay faults. Experimental results for the IS- CAS benchmark circuits are presented to demonstrate the effectiveness of the proposed method.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125293817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC 片上/片外总线桥的设计复用,实现基于amba的SoC的高效测试访问
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.13
Jaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park
{"title":"Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC","authors":"Jaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park","doi":"10.1109/ATS.2007.13","DOIUrl":"https://doi.org/10.1109/ATS.2007.13","url":null,"abstract":"This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128835313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis ir下降对路径延迟测试的影响
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.89
Chunsheng Liu, Yang Wu, Yu Huang
{"title":"Effect of IR-Drop on Path Delay Testing Using Statistical Analysis","authors":"Chunsheng Liu, Yang Wu, Yu Huang","doi":"10.1109/ATS.2007.89","DOIUrl":"https://doi.org/10.1109/ATS.2007.89","url":null,"abstract":"IR-drop has become a major source of delay defects in deep sub-micron VLSI designs. In this work, we analyze the effect of IR-drop in path-delay test and how to obtain more accurate delay information of critical paths. For possible regions with IR-drop, we perform timing analysis on these nodes such that a certain amount of voltage drop can be associated with extra delays on victim nodes. Power analysis is conducted to determine the occurrence probability of a certain voltage drop. These probability values are used to weigh the extra delays caused by IR-drop of all victim nodes, which are then accumulated along each path. Experimental results show that such a process can effectively take the small delays caused by IR-drop into consideration and can have a significant impact on the identification and analysis of critical paths.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Invited Talk 2: EDA to the Rescue of the Silicon Roadmap 特邀演讲2:EDA拯救硅路线图
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.108
T. Williams
{"title":"Invited Talk 2: EDA to the Rescue of the Silicon Roadmap","authors":"T. Williams","doi":"10.1109/ATS.2007.108","DOIUrl":"https://doi.org/10.1109/ATS.2007.108","url":null,"abstract":"Since the invention of the transistor nearly six decades ago, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling fulfilling the promise and industry-defining mantra of \"smaller, faster, cheaper!\", and harder to Test. Now, in the realm of 65- and 45-nanometer design and manufacturing the industry is confronted by multiple complex and stubborn challenges: silicon technology keeps shrinking but doesn't advance in speed at the same rate. The recent high-k dielectric announcements have yet to be proven manufacturable, and copper interconnect is already hitting the wall. We are driving to the edge of the silicon roadmap, but there is no viable alternative to CMOS within our reach. Not coincidentally, several companies are announcing their intention to stop internal R&D at the 45 nanometer node and use foundry-supplied processes at 32 nanometers and below. The electronics industry ecosystem is at a fork in the road: those few who can afford it will keep rushing to 45 nanometers and maybe beyond, to 32 and 25 nanometers; the rest will hold at 130 or perhaps 90 nanometers, trying to get the most out of those processes that they can. In both cases it is EDA that will come to the rescue. This is true for the Test area as well. We will show how new tools in test will be needed to keep up with these very hard requirements and how EDA Teat can help. EDA innovation is the gear that enables design for manufacturing and yield (which encompasses design for test), design for low power, and design for variability. EDA is not only the enabler for quality in electronic design; it is truly \"where electronics begins.\"","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bluetooth Hopping BER Testing Methodologies on a Production Test Platform 生产测试平台上的蓝牙跳变误码率测试方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.44
David Bement, David Karr
{"title":"Bluetooth Hopping BER Testing Methodologies on a Production Test Platform","authors":"David Bement, David Karr","doi":"10.1109/ATS.2007.44","DOIUrl":"https://doi.org/10.1109/ATS.2007.44","url":null,"abstract":"Bluetooth devices are required to meet specific levels for Bit Error Rate (BER) performance. Two approaches to implementing a Bluetooth BER test with Frequency Hopping in a production ATE environment will be discussed.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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