K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li, V. Chickermane
{"title":"低功耗减少引脚数测试方法","authors":"K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li, V. Chickermane","doi":"10.1109/ATS.2007.81","DOIUrl":null,"url":null,"abstract":"This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low Power Reduced Pin Count Test Methodology\",\"authors\":\"K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li, V. Chickermane\",\"doi\":\"10.1109/ATS.2007.81\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.\",\"PeriodicalId\":289969,\"journal\":{\"name\":\"16th Asian Test Symposium (ATS 2007)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"16th Asian Test Symposium (ATS 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2007.81\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Asian Test Symposium (ATS 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2007.81","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.
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