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EHSAT Modeling from Algorithm Description for RTL Model Checking 基于算法描述的RTL模型检测EHSAT建模
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.92
Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao
{"title":"EHSAT Modeling from Algorithm Description for RTL Model Checking","authors":"Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao","doi":"10.1109/ATS.2007.92","DOIUrl":"https://doi.org/10.1109/ATS.2007.92","url":null,"abstract":"This paper presents a new method to translate Verilog HDT into RTL Model combining algorithm description for high level verification. The model could be used in the enhanced version of a state-of-the-art finite-domain satisfiability (SAT) solver EHSAT to check the verified properties. The enhanced version of EHSAT provides an efficient algorithm to solve the SAT problem for higher level abstraction RTL designs using a hybrid branch-and-bound strategy with conflict-driven learning. This modeling program analyses the control flow of Verilog source codes and generates corresponding statements for the enhanced version EHSAT. This method could largely reduce the scale of model checking and simplify the devices used in EHSAT. Experimental results show that this method can reduce verification problem sizes considerably while comparing with lower level methods.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128213393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Using FPGA configuration memory to accelerate yield learning for advanced process 利用FPGA组态存储器加速高级制程的良率学习
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.24
Jenny Fan, Xiao-Yu Li, I. Hartanto
{"title":"Using FPGA configuration memory to accelerate yield learning for advanced process","authors":"Jenny Fan, Xiao-Yu Li, I. Hartanto","doi":"10.1109/ATS.2007.24","DOIUrl":"https://doi.org/10.1109/ATS.2007.24","url":null,"abstract":"The configuration memory is irregularly placed in a FPGA (Field Programmable Gate Array) chip and physically attached to the programmable logic circuits. This type of memory is more powerful than standard SRAM to monitor random or systematic process defects because the configuration memory test catches defects in both the memory cell and logic circuits. This paper will demonstrate a methodology of using this capability to accelerate yield learning for advanced process.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Symbolic Path Sensitization Analysis and Applications 符号路径敏化分析与应用
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.21
Jian Kang, S. Seth, Shashank K. Mehta
{"title":"Symbolic Path Sensitization Analysis and Applications","authors":"Jian Kang, S. Seth, Shashank K. Mehta","doi":"10.1109/ATS.2007.21","DOIUrl":"https://doi.org/10.1109/ATS.2007.21","url":null,"abstract":"A new symbolic approach models the sensitization paths to selected primary output(s) as Boolean equations, with satisfying solutions representing the set of all sources of single and multiple sensitizations in the circuit. The paper discusses two applications of this idea: model-free fault diagnosis and input sensitization analysis.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132014192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Diagnostic Test Generation Targeting Equivalence Classes 针对等价类的诊断测试生成
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.15
I. Pomeranz, S. Reddy
{"title":"Diagnostic Test Generation Targeting Equivalence Classes","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2007.15","DOIUrl":"https://doi.org/10.1109/ATS.2007.15","url":null,"abstract":"We describe a diagnostic test generation procedure that targets the equivalence classes of the test set as it is being generated, instead of considering one fault pair at a time (an equivalence class contains faults that are indistinguished by the test set). When an equivalence class is targeted, all the fault pairs in the equivalence class are targeted simultaneously. This reduces the number of test generation targets, and as a result, it reduces the number of tests in the final test set as well as the test generation time. The implementation of the diagnostic test generation procedure is based on a test elimination process that can accommodate equivalence classes of any size.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129413090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Top 5 Issues in Practical Testing of High-Speed Interface Devices 高速接口器件实际测试中的五大问题
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.122
T.J. Yamaguchi
{"title":"Top 5 Issues in Practical Testing of High-Speed Interface Devices","authors":"T.J. Yamaguchi","doi":"10.1109/ATS.2007.122","DOIUrl":"https://doi.org/10.1109/ATS.2007.122","url":null,"abstract":"Recently very different ways have been proposed to perform jitter testing of high-speed physical layer ICs in an HV production testing environment.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114522813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Improved Test Case Generation Method of Pair-Wise Testing 一种改进的成对测试用例生成方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.65
Qian Feng-an, Jiang Jian-hui
{"title":"An Improved Test Case Generation Method of Pair-Wise Testing","authors":"Qian Feng-an, Jiang Jian-hui","doi":"10.1109/ATS.2007.65","DOIUrl":"https://doi.org/10.1109/ATS.2007.65","url":null,"abstract":"Pair-wise testing is a testing criterion based on specification, which requires that for each pair of parameters, every combination of their valid value should be covered by at least one test case in the test set. This paper presents an improved method based on AETG. Experimental results show that the size of test set produced by our method is relatively small. In addition, the method can be easily implemented.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"797 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Test Education in the Global Economy 全球经济中的考试教育
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.110
Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu
{"title":"Test Education in the Global Economy","authors":"Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu","doi":"10.1109/ATS.2007.110","DOIUrl":"https://doi.org/10.1109/ATS.2007.110","url":null,"abstract":"Summary form only given. There is an increasing demand for test and diagnosis expertise in the global semiconductor industry, in sectors ranging from foundries to test houses, to IDM companies, and from fabless design houses to EDA companies. Test education, however remains a niche, highly specialized subject area in the graduate curriculum and is seldom covered in undergraduate classes. In this panel, we evaluate the current health of academic test education and debate the role and goals of future test education, as well as those changes that need to be made to meet the global market demands.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128680419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture 多模分割扫描结构下LOS转换测试的测试数据和测试时间缩短
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.33
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li
{"title":"Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture","authors":"Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li","doi":"10.1109/ATS.2007.33","DOIUrl":"https://doi.org/10.1109/ATS.2007.33","url":null,"abstract":"Launch-off-Shift (LOS) is a widely used technique for delay test in scan-based design. Test data compression for LOS patterns, however, is less efficient. In this paper, we first analyze the reason for low compression rate in LOS patterns, and present an LOS test enabled scan architecture that supports three operation modes: broadcast, multicast, and serial. Efficient LOS test data compression can be achieved under this architecture with limited hardware overhead. An ATPG method for LOS test patterns under the proposed architecture is also presented. Experimental results show that most of the serial scan operations can be replaced by multicast operations, and thus achieve much better compression rate.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Test and Diagnosis Methodology for RF Transceivers 射频收发器的测试与诊断方法
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.29
Hungkai Chen, C. Su
{"title":"A Test and Diagnosis Methodology for RF Transceivers","authors":"Hungkai Chen, C. Su","doi":"10.1109/ATS.2007.29","DOIUrl":"https://doi.org/10.1109/ATS.2007.29","url":null,"abstract":"This paper proposes an RF test and diagnosis methodology based on digital DFT structure and built- in DSP function of a SoC Chip. Constellation variation plots are proposed to identify the faulty component. Furthermore, linear interpolation is used to determine the amount of variation. The simulated test results show that the method is able to identify not only the faulty component but also the variation amount precise.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121852181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits 同时开关噪声对数字CMOS电路静态性能的影响
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.73
F. Azaïs, Laurent Larguier, M. Renovell
{"title":"Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits","authors":"F. Azaïs, Laurent Larguier, M. Renovell","doi":"10.1109/ATS.2007.73","DOIUrl":"https://doi.org/10.1109/ATS.2007.73","url":null,"abstract":"This paper analyzes the logic errors in digital circuits due to the presence of simultaneous switching noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called 'minimum switch condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called 'signal coherence condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124211507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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