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16th Asian Test Symposium (ATS 2007)最新文献

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Using Programmable On-Product Clock Generation (OPCG) for Delay Test 使用可编程产品上时钟生成(OPCG)进行延迟测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.76
B. Keller, A. Uzzaman, Bibo Li, T. Snethen
{"title":"Using Programmable On-Product Clock Generation (OPCG) for Delay Test","authors":"B. Keller, A. Uzzaman, Bibo Li, T. Snethen","doi":"10.1109/ATS.2007.76","DOIUrl":"https://doi.org/10.1109/ATS.2007.76","url":null,"abstract":"On-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, but it is a labor-intensive process to identify the cut- points and the OPCG behavior so the ATPG tools can ignore the OPCG logic. Supporting programmable OPCG logic in an ASIC methodology flow required us to automate the OPCG test generation flow. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and show some results for a few real designs.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127865599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits CMOS电路延迟故障检测的在线BIST技术
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.100
Elham K. Moghaddam, S. Hessabi
{"title":"An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits","authors":"Elham K. Moghaddam, S. Hessabi","doi":"10.1109/ATS.2007.100","DOIUrl":"https://doi.org/10.1109/ATS.2007.100","url":null,"abstract":"This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114187453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scan Diagnosis and Its Successful Industrial Applications 扫描诊断及其成功的工业应用
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.99
Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, R. Klingenberg
{"title":"Scan Diagnosis and Its Successful Industrial Applications","authors":"Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, R. Klingenberg","doi":"10.1109/ATS.2007.99","DOIUrl":"https://doi.org/10.1109/ATS.2007.99","url":null,"abstract":"As technologies move below 130nm, the IC industry has seen a significant change in defect type encountered. Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnosis targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The ranked, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. This presentation briefly explains the technology behind the scene, discusses scan diagnosis applications and shows the results.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Scheduling for Memory Cores with Built-In Self-Repair 具有内置自我修复功能的内存核的测试调度
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.26
T. Yoneda, Yuusuke Fukuda, H. Fujiwara
{"title":"Test Scheduling for Memory Cores with Built-In Self-Repair","authors":"T. Yoneda, Yuusuke Fukuda, H. Fujiwara","doi":"10.1109/ATS.2007.26","DOIUrl":"https://doi.org/10.1109/ATS.2007.26","url":null,"abstract":"This paper presents a stage-based test scheduling for memory cores with BISR scheme under power constraint. We introduce a model to compute the expected test time for a given test schedule for memory cores with BISR scheme based on pass probabilities, and propose a test scheduling algorithm to minimize the expected test time. Experimental results show a significant expected test time reduction compared to the core-based test scheduling method which minimizes the test time.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125336265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods 使用NIST和小波变换方法的可编程增益放大器测试点选择
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.28
Xinsong Zhang, S. Ang, C. Carter
{"title":"Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods","authors":"Xinsong Zhang, S. Ang, C. Carter","doi":"10.1109/ATS.2007.28","DOIUrl":"https://doi.org/10.1109/ATS.2007.28","url":null,"abstract":"Test point selections for a programmable gain amplifier (PGA) using the National Institute of Standard (NIST) and wavelet transform methods are investigated. Although the wavelet transform method is an efficient method in test point selection for many mixed-signal devices, for a PGA with 31 input steps, the NIST method is shown to be more accurate in predicting the output gain responses than the wavelet transform method.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125952125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing 一种多时钟速度测试的片上测试时钟控制方案
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.61
Xiaoxin Fan, Yu Hu, Laung-Terng Wang
{"title":"An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing","authors":"Xiaoxin Fan, Yu Hu, Laung-Terng Wang","doi":"10.1109/ATS.2007.61","DOIUrl":"https://doi.org/10.1109/ATS.2007.61","url":null,"abstract":"To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed. However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter-clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126858355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Keynote Speech 1: New Paths for Test 主题演讲1:测试的新途径
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.105
J. Abraham
{"title":"Keynote Speech 1: New Paths for Test","authors":"J. Abraham","doi":"10.1109/ATS.2007.105","DOIUrl":"https://doi.org/10.1109/ATS.2007.105","url":null,"abstract":"Summary form only given.Test techniques for screening defective integrated circuits (ICs) after manufacture have to consider potential defects as well as the cost. In the future, test must deal with trends including advances in IC technology which continue to reduce feature sizes, the fact that mixed-signal systems on a chip are becoming a larger fraction of the semiconductor market, and very high transistor densities as well as new transistor technologies which loom over the horizon. This talk will explore the significant impact that these trends will have on the future of test. Test approaches for digital circuits have to deal with failures which are no longer just logic level, and test techniques have to address embedded mixed-signal and RF modules. In addition, with the very large number of potential devices on a chip, test will have to begin to address tolerating defects or on-chip repair for reasonable yields. Some possible directions which show promising solutions to these problems will also be described.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126424913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Review of Power Strategies for DFT and ATPG DFT和ATPG的功率策略综述
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.88
B. Keller, Tom Jackson, A. Uzzaman
{"title":"A Review of Power Strategies for DFT and ATPG","authors":"B. Keller, Tom Jackson, A. Uzzaman","doi":"10.1109/ATS.2007.88","DOIUrl":"https://doi.org/10.1109/ATS.2007.88","url":null,"abstract":"This paper presents a review of power topics for DFT and ATPG. The issue of increasing power in ASIC design is an important topic.in terms of power management and CMOS power consumption has been considered as low-power. The related issues of power and test have been discussed, but often in the fairly narrow context of limiting power during scan test. This topic is becoming increasingly important as power management strategies within chips become more common and complex and at-speed test becomes more important for detecting defects which escape the classical stuck-at model. Increasingly chips incorporate features to allow active power management.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Programmable Scan-Based Logic Built-In Self Test 基于可编程扫描的逻辑内置自测试
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.45
Liyang Lai, Wu-Tung Cheng, T. Rinderknecht
{"title":"Programmable Scan-Based Logic Built-In Self Test","authors":"Liyang Lai, Wu-Tung Cheng, T. Rinderknecht","doi":"10.1109/ATS.2007.45","DOIUrl":"https://doi.org/10.1109/ATS.2007.45","url":null,"abstract":"This paper presents a programmable approach for performing scan-based logic built-in self test. This approach combines the techniques of reseeding and weighted random patterns testing. Reseeding is used to encode the bias cube and weighted patterns are used to fine tune the weight set. Experimental results show fault coverage comparable to ATPG can be achieved. Most importantly, the scheme fits well in the system test environment and high fault coverage can be obtained with a small number of reconfigurations on the BIST controller.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrated Test Solution for embedded UHF/RF SOC 嵌入式UHF/RF SOC集成测试解决方案
16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI: 10.1109/ATS.2007.117
S. Lu, Dee-Won Lee
{"title":"Integrated Test Solution for embedded UHF/RF SOC","authors":"S. Lu, Dee-Won Lee","doi":"10.1109/ATS.2007.117","DOIUrl":"https://doi.org/10.1109/ATS.2007.117","url":null,"abstract":"Modern SOC is trending towards high level integration, UHF/ RF blocks have gradually found their positions in the integration puzzle, such as digital video decoder with integrated satellite set-top box UHF receiver, DOCSIS cable modem with integrated CMOS tuner. Instead of adding 6-digits capital investment to upgrade the ATE system with full-spectrum RF test option and retrain mixed signal test engineer to be fluent with RF terminology, this paper explores an alternate approach of combining a \"familiar\" bench RF signal generator with standard mixed-signal test configuration to provide a \"just-enough\" test solution for embedded UHF and RF SOC ICs. The external RF signal generator is not new to ATE world, it has been used as alternate master clock for multi-clock domain ATE system, and now it finds its new position as a low-cost accurate RF source to test UHF/RF blocks which only require a programmable RF stimulus. The RF signal generator can provide a wide frequency range and low output power with outstanding phase-noise performance and analog modulation features. It can be easily integrated with ATE system with high bandwidth co-ax cable and accessible to DUT through pogo pins. The insertion loss calibration of this RF source can be done through PCB pattern coupler on the DUT board with either high speed digitizer or high bandwidth sampler. The output power and frequency of this RF source can be easily controlled through GPIB SICL library call in the test program. The presentation details two UHF tests utilizing this RF source: 1-dB compression test and input sensitivity test. The test performance and test time are discussed.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131342012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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