CMOS电路延迟故障检测的在线BIST技术

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI:10.1109/ATS.2007.100

Elham K. Moghaddam, S. Hessabi

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引用次数: 1

摘要

本文对CMOS逻辑电路中的延迟故障测试进行了仿真研究。提出了一种新的内置自检测技术来检测该逻辑族中的延迟故障。该方案不需要生成测试模式，可用于鲁棒在线测试。给出了面积、延迟和功耗开销的仿真结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits

This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.

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16th Asian Test Symposium (ATS 2007)

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