A Review of Power Strategies for DFT and ATPG

Abstract

This paper presents a review of power topics for DFT and ATPG. The issue of increasing power in ASIC design is an important topic.in terms of power management and CMOS power consumption has been considered as low-power. The related issues of power and test have been discussed, but often in the fairly narrow context of limiting power during scan test. This topic is becoming increasingly important as power management strategies within chips become more common and complex and at-speed test becomes more important for detecting defects which escape the classical stuck-at model. Increasingly chips incorporate features to allow active power management.