{"title":"Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test","authors":"S. Taneja","doi":"10.1109/ATS.2007.106","DOIUrl":null,"url":null,"abstract":"Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production. The Test technologies need to innovate at a faster pace to enable system companies and their semiconductor suppliers - in segments ranging from automotive to entertainment and multi-media to meet these new challenges. The rapid advances in nanometer technologies pose another set of challenges, primarily related to integration. Whereas the integration at the level of interoperability amongst different tools in the design and implementation flows has been adequate in the past, nanometer technology introduces new levels of complexity due to the advanced physics effects and higher scales of transistor integration. This in turn results in complex interaction and interdependence amongst the different design steps such as synthesis, test, floor planning, placement, routing and chip finishing. The EDA industry needs to establish a new paradigm and a \"deep integration\" to meet these challenges and to deliver the productivity gains that will enable our customers to meet demands on functionality, correctness, quality and time-to-volume production. The paradigm needs to shift from \"Design For Test\" to \"Design With Test\", to fully model the tight interdependencies between design and test. During the design phase, DFT steps must integrate well during the design architecture, synthesis, timing and layout steps. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using timing and layout information. Such advances in innovation and integration will go a long way in moving the EDA industry from being a supplier of point tools to the role of a partner proactively anticipating and delivering on customers' needs. The keynote will discuss these challenges and possible solutions and scenarios.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Asian Test Symposium (ATS 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2007.106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production. The Test technologies need to innovate at a faster pace to enable system companies and their semiconductor suppliers - in segments ranging from automotive to entertainment and multi-media to meet these new challenges. The rapid advances in nanometer technologies pose another set of challenges, primarily related to integration. Whereas the integration at the level of interoperability amongst different tools in the design and implementation flows has been adequate in the past, nanometer technology introduces new levels of complexity due to the advanced physics effects and higher scales of transistor integration. This in turn results in complex interaction and interdependence amongst the different design steps such as synthesis, test, floor planning, placement, routing and chip finishing. The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges and to deliver the productivity gains that will enable our customers to meet demands on functionality, correctness, quality and time-to-volume production. The paradigm needs to shift from "Design For Test" to "Design With Test", to fully model the tight interdependencies between design and test. During the design phase, DFT steps must integrate well during the design architecture, synthesis, timing and layout steps. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using timing and layout information. Such advances in innovation and integration will go a long way in moving the EDA industry from being a supplier of point tools to the role of a partner proactively anticipating and delivering on customers' needs. The keynote will discuss these challenges and possible solutions and scenarios.