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Mission Smart Production1 任务智能生产
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948782
M. Brummayer, S. Fuchshumer
{"title":"Mission Smart Production1","authors":"M. Brummayer, S. Fuchshumer","doi":"10.1109/ESSDERC.2014.6948782","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948782","url":null,"abstract":"New technologies and tools are among the most important ways of covering the technological gap required in process optimization and increased competitiveness. Where conventional techniques are mature and robust enough to guarantee stable performance, smart production should contribute to developing more flexible, cost optimal and environmental friendly production processes. Powerful ICT (Information and Communication Technology) solutions are an important enabler towards smart steelmaking processes. In this context important relevant future challenges and opportunities in the steel industry will be discussed and selected applications in steelmaking processes will be presented.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128506743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies 间隔区对解释28nm Bulk和FDSOI技术中短通道迁移率崩溃的重要性
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948808
F. Monsieur, Y. Denis, D. Rideau, V. Quenette, G. Gouget, C. Tavernier, H. Jaouen, G. Ghibaudo, J. Lacord
{"title":"The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies","authors":"F. Monsieur, Y. Denis, D. Rideau, V. Quenette, G. Gouget, C. Tavernier, H. Jaouen, G. Ghibaudo, J. Lacord","doi":"10.1109/ESSDERC.2014.6948808","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948808","url":null,"abstract":"This work focuses on what drives the access resistance. Based on TCAD simulations, we evidence that the access resistance does depend on gate voltage. From this statement, after considering an access resistance compact model, we show that the access resistance voltage dependence generates an artificial short channel mobility collapse. Based on actual silicon data we establish link between μo-L and Rac-Vg. In particular this relation predicts that negative resistance could be extracted for narrow devices in agreement with experiments.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Dual Ground Plane EDMOS in ultrathin FDSOI for 5V energy management applications 用于5V能量管理应用的超薄FDSOI双地平面EDMOS
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948776
Antoine Litty, S. Ortolland, D. Golanski, S. Cristoloveanu
{"title":"Dual Ground Plane EDMOS in ultrathin FDSOI for 5V energy management applications","authors":"Antoine Litty, S. Ortolland, D. Golanski, S. Cristoloveanu","doi":"10.1109/ESSDERC.2014.6948776","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948776","url":null,"abstract":"A promising high-voltage MOSFET (HVMOS) in Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB-FDSOI) is experimentally demonstrated. The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. We show that the separated biasing of the two ground planes enables independent control of the channel and drift regions. Electrical characteristics such as specific on-resistance/breakdown trade-off as a function of the back-gate voltage and geometry are explored. We present and discuss encouraging results for 5V switched mode applications for energy management.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129758175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Superior performance and Hot Carrier reliability of Strained FDSOI nMOSFETs for advanced CMOS technology nodes 用于先进CMOS技术节点的应变FDSOI nmosfet的优越性能和热载流子可靠性
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948801
G. Besnard, X. Garros, F. Andrieu, P. Nguyen, W. V. D. Daele, P. Reynaud, W. Schwarzenbach, D. Delprat, K. Bourdelle, G. Reimbold, S. Cristoloveanu
{"title":"Superior performance and Hot Carrier reliability of Strained FDSOI nMOSFETs for advanced CMOS technology nodes","authors":"G. Besnard, X. Garros, F. Andrieu, P. Nguyen, W. V. D. Daele, P. Reynaud, W. Schwarzenbach, D. Delprat, K. Bourdelle, G. Reimbold, S. Cristoloveanu","doi":"10.1109/ESSDERC.2014.6948801","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948801","url":null,"abstract":"The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
InGaAs inversion layers band structure, electrostatics, and mobility modeling based on 8 Band k · p theory 基于8波段k·p理论的InGaAs逆温层能带结构、静电学和迁移率建模
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948771
A. Pham, Seonghoon Jin, W. Choi, M. J. Lee, S. Cho, Y.-T. Kim, K. Lee, Y. Park
{"title":"InGaAs inversion layers band structure, electrostatics, and mobility modeling based on 8 Band k · p theory","authors":"A. Pham, Seonghoon Jin, W. Choi, M. J. Lee, S. Cho, Y.-T. Kim, K. Lee, Y. Park","doi":"10.1109/ESSDERC.2014.6948771","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948771","url":null,"abstract":"8 band k · p method is used to calculate subband structures of InGaAs inversion layers accounting for strong coupling between conduction and valence bands around Γ point as well as quantum confinement. Inversion layer mobility is computed employing Kubo-Greenwood formalism. Scatterings due to acoustic phonons, polar optical phonons, ionized impurities, interface fixed charges, surface roughness, and alloy disorder are included. The simulated low-field electron mobility results are in good agreement with in-house experimental data with and without an InP capping layer.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123013566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaN virtual prototyping: From traps modeling to system-level cascode optimization GaN虚拟原型:从陷阱建模到系统级级级代码优化
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948829
G. Curatola, Andreas Kassmanhuber, S. Yuferev, J. Franke, G. Pozzovivo, S. Lavanga, G. Prechtl, T. Detzel, O. Haeberlen
{"title":"GaN virtual prototyping: From traps modeling to system-level cascode optimization","authors":"G. Curatola, Andreas Kassmanhuber, S. Yuferev, J. Franke, G. Pozzovivo, S. Lavanga, G. Prechtl, T. Detzel, O. Haeberlen","doi":"10.1109/ESSDERC.2014.6948829","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948829","url":null,"abstract":"The present paper focuses on the system-level optimization of GaN technology for high voltage applications. We will show that a key requirement for the future success of the GaN technology is the full system-optimization achieved by a simultaneous optimization of technology, packaging and applications. We will also show that Virtual Prototyping (VP) becomes, in GaN technology, a fundamental tool that allows not only to have a fundamental understanding of the device properties but more importantly it allows to strongly link device optimization, technology and system-level performance. In the present paper we will describe our view on the system-level optimization of high voltage GaN technology and present detailed simulations and comparison with experiments for both normally on isolated GaN transistors and cascoded GaN devices in real switching applications.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130256815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Blue selective photodiodes for optical feedback in LED wafer level packages 用于LED晶圆级封装的光反馈的蓝色选择性光电二极管
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948788
Z. Esfahani, T. Ma, H. W. Zeijl, G. Q. Zhang, A. Rostamian, M. Kolahdouz
{"title":"Blue selective photodiodes for optical feedback in LED wafer level packages","authors":"Z. Esfahani, T. Ma, H. W. Zeijl, G. Q. Zhang, A. Rostamian, M. Kolahdouz","doi":"10.1109/ESSDERC.2014.6948788","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948788","url":null,"abstract":"Recently applying an intelligent self-curing system to get a feedback from the LED light in order to control its intensity with driving current has attracted so much attention. This study presents a silicon stripe-shaped photodiode which is successfully designed and fabricated using a 2μm BiCMOS process. This process flow integrates simultaneously the photodiodes, the CMOS and BJT transistors all in just five masks. In this cheap and smart wafer level LED packaging, fabricated photodiodes demonstrated a very high selectivity to blue light. The maximum responsivity is at 480nm which is matched with the blue LED's illumination. The single-stripe photodiodes due to their higher rate of recombination caused by the dead layer formation at the surface showed lower responsivity compared to multi-stripe ones. The fabricated devices presented a two-fold increase in the responsivity and quantum efficiency compared to previously published sensors.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High Ion/Ioff ratio BJT selector for 32 cell string Resistive RAM arrays 用于32单元串电阻式RAM阵列的高离子/开关比BJT选择器
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948804
A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli, A. Benvenuti
{"title":"High Ion/Ioff ratio BJT selector for 32 cell string Resistive RAM arrays","authors":"A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli, A. Benvenuti","doi":"10.1109/ESSDERC.2014.6948804","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948804","url":null,"abstract":"A compact low leakage selector is needed for any resistive RAM arrays to enable the correct memory operation. In particular Phase Change Memories are demanding in terms of trade off between low leakage and driving current capability due to the Joule-heating-based programming mechanism. This work addresses a full integration path for optimizing bipolar junction transistor (BJT) to realize long string of base-emitter junctions up to 32, enabling the reduction of the base straps overhead thus further reducing the effective array size in respect to conventional approach. The optimization between the base resistance value and base-emitter leakage is not trivial and it has been performed by working on junction position and process thermal budget mainly by TCAD. Experimental validation has been provided on a 45 nm PCM vehicle, demonstrating the feasibility of the proposed approach.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130070385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of high-voltage charge-trapping effects in GaN-based power HEMTs 氮化镓基功率hemt中高压电荷俘获效应的表征
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948842
D. Bisi, A. Stocco, M. Meneghini, F. Rampazzo, A. Cester, G. Meneghesso, E. Zanoni
{"title":"Characterization of high-voltage charge-trapping effects in GaN-based power HEMTs","authors":"D. Bisi, A. Stocco, M. Meneghini, F. Rampazzo, A. Cester, G. Meneghesso, E. Zanoni","doi":"10.1109/ESSDERC.2014.6948842","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948842","url":null,"abstract":"We investigate the effects and the causes of highvoltage charge-trapping phenomena in AlGaN/GaN Schottky-HEMTs grown on SiC substrate, and we present an high-voltage pulsed system, implemented by a cost-effective fully-customable modular solution. The characterization methodology includes double-pulsed ID-VD measurements, time-resolved RON recovery transients, and leakage-currents analysis. The observed parasitic dynamic RON-increase is triggered by high drain-voltage (>50V), and likely originates from the trapping of parasitic electrons supplied by leakage currents at the crystallographic defect-states located within the epitaxial structure.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of quantum modulation of the inversion charge in the MOSFET subthreshold regime 量子调制对MOSFET亚阈区反转电荷的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948816
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
{"title":"Impact of quantum modulation of the inversion charge in the MOSFET subthreshold regime","authors":"G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo","doi":"10.1109/ESSDERC.2014.6948816","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948816","url":null,"abstract":"In this work, the impact of quantum modulation of the charge in the subtreshold regime is investigated for various architectures. Using Hänsch's model, the reduction in threshold voltage roll-off induced by quantum effects in a double gate is investigated. Next, it is demonstrated with Poisson-Schrödinger simulations that there is a quantum-induced increase in sub-threshold swing for an InAs channel compared to a Si channel in a long-channel bulk device. Finally, a correction to the Bulk subthreshold swing classical model is proposed and validated on simulations. The results suggest that, contrary to double-gate devices, quantum modulation of the charge has an impact in the subthreshold regime for bulk architectures.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121612808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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